SU1254486A1 - Device for interrupting programs - Google Patents

Abstract

The invention relates to computing, namely, devices for interrupting programs when interfacing various external devices with digital computers. The aim of the invention is to reduce hardware costs. The goal is achieved by the fact that the device containing the protection register, the encoder, the output element OR, the mode trigger, the input element AND, the N prergaani channels, each of which "i Jitfi. - e contains an interrupt trigger, a control trigger and four elements And, a reset register and a number of additional links are entered. Improving the reliability of program interrupt processing is achieved by connecting the second input of the input element I with the input of the device response and the second input of the mode trigger with the control input of the device, which ensures a change in the algorithm for blocking the arrival in the DVM of interrupt signals in the operation mode with relative priorities . Introduction of the reset register and connection of its inputs with the outputs of the second elements I, and outputs with the first inputs of the interrupt channel control triggers and the corresponding clocking of the reset register with the response and control signals reduced the number of communication lines with the digital computer and eliminated one element in each interrupt channel. 1 il. (L

Description

The invention relates to computing, namely, devices for interrupting programs when interfacing various external devices with digital computers.

The purpose of the invention is to reduce the number of external communications and equipment. I

The drawing shows a functional diagram of the device for the prergo programs.

The device contains a protection register 1, an encoder 2, an OR element 3, a trigger 4, an AND element 5, a reset register 6, channels 7, each of which includes elements AND 8-11, a trigger 12, a trigger 13, a control mode input 14. - devices of my device, device code input group 15, device response input 16, device signal input 17, device request input group 18, device interrupt output 19, device interrupt address code output group 20.

The maintenance of external requests with absolute priorities by providing eTCfi with the enabled output potential of the trigger 4 mode, which is reset to the zero state when the device is turned on and its installation in the single state is blocked by the inhibitory potential at the mode control input 14.

In the initial state, the resolving potential from the outputs of the control trigger 12 of each channel is allowed to receive external requests coming in through group 18 of inputs through AND 8 and fixed by the trigger 13 Output potential from trigger 13 is set to the corresponding trigger 12, the output of which is at the inputs

The mode of operation with relative priorities is provided by the resolvable potential at the input 14 of the mode control. After switching on the device, trigger 4 is set to the zero state and has a potential at the output of permissions. In response to an interrupt signal, given by the device, the digital computer on input 16 generates a response signal, which, together with the interrupt signal and the signal on input 14, sets the mode trigger to a single state, which is prohibited by

Elements 8 is blocked from receiving the corresponding external request. Sig-interrupts in the CMM of interrupt signals.

fillers with triggers. 12 and 13 and register 1 are fed to the inputs of AND elements 9 and 10, which highlight the request having the highest priority, and ensure the end-to-end transmission of the interrupt inhibit signal from the highest priority level to the lowest one. Request priorities are reduced from left to right in the order of channel numbering 7.

Thus, the interrupt signal is generated only at the output of the element And 10, the highest priority at the current time point of channel 7. This

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all levels of priorities. The mode trigger 4 is reset to the zero state upon completion of the interrupt program by a signal received at input 17. The external request is received by the digital computer for execution with a higher priority among all received by the device. At the same time, it is blocked by a response signal until the service is completed

request.

Claims (1)

Invention Formula A device for interrupting a program containing a register 9A1Cnts, vshfrator. five 0 the signal is fed to the input of the element OR 3, to the input of the decoder 2, to the input of the register 6 and to the first input of the element 11 of the corresponding channel. At the output of the element OR 3, a signal is formed, and at the output of the encoder 2, a transition command, which is fed to the digital computer. After receiving the transition command of the digital computer via input 16, it generates a signal controlling the recording of values from the outputs of elements 10 of each channel into register 6 and setting to zero the trigger 13 of the channel currently operating. Triggers 12 store external requests until they are completely executed and, through element 9, prohibit the entry of external requests into the digital computers of lower priorities. The triggers 12 are set to zero state at the end of the program caused by an external request, for which the program provides a signal from the digital computer via input 17, which, arriving at the second input of the register with 5 reset, opens its outputs and generates a reset signal of the corresponding trigger 12. Thus, at the input of the element And 8 and at the inputs of the element And 9 it is established that the potential, i.e. the blocking of requests of the lowest priority level is removed and the highest of them goes to the digital computer. The operation mode with relative priorities is provided by permitting the potential at input 14 of mode control. After switching on the device, trigger 4 is set to the zero state and has a potential at the output of permissions. In response to the interrupt signal, emitted by the device, the digital computer on input 16 generates a response signal, which, together with the interrupt signal and the signal on input 14, sets the mode trigger to one state, which prohibits five 0 step in the CMP interrupt signals. all levels of priorities. The mode trigger 4 is reset to the zero state upon completion of the interrupt program by a signal received at input 17. The external request is received by the digital computer for execution with a higher priority among all received by the device. At the same time, it is blocked by a response signal until the service is completed request. Invention Formula A device for interrupting programs, comprising a register of 9-1 cents, into a code. the OR element, the trigger, the AND element, the channels, each of which contains two triggers and four AND elements, each device's request input connected to the first input of the first signal And the channel of the same name, in each channel the output of the first element Well connected to the single input of the first trigger, the output of the second element And is connected to the first input of the third element And, a single input of the second trigger is connected to the output of the first trigger and the first input of the second element And, the second input of which is connected to the first input of the fourth element the second input of which is connected to the inverse output of the second trigger and the second input of the first element AND, the output of the third element AND is connected to the zero input of the first trigger, the output of the second element AND of each channel is connected to the corresponding input of the encoder and the corresponding input of the element OR, the second input of the third element And each channel is connected to the response input of the device, the third input of the second element AND of each channel is connected to the same output of the security register, the inputs of which are connected to the code input group The device’s second inputs, the second input of the first channel element AND, are connected to the trigger output, the unit input of which is connected to the output of the AND element, the first input of which is connected to the output of the OR element and the output of the device's primary interface, the second input of the AND element is connected to the control input of the device mode connected to the output group of the device address address code, characterized in that, in order to reduce the number of external communications and equipment, a reset register is entered into it, the write control input of which is connected with a response input of the device and with the third input of the element I, the control input of the register is connected to the zero input of the trigger and to the signal input of the device, the outputs of the second elements AND of the channels are connected to the inputs of the reset register, and the first input of the second trigger of each channel is connected to the same the output of the reset register, the third inputs of the fourth element AND of each channel, starting from the second, are connected to the outputs of the fourth element AND of the previous channel. Editor I. Casarda Compiled by M, Kudr Shev Tehred I.Popovich Proofreader M. Demchik Order 4722/53 Circulation 671. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 / w w t