SU1660002A2 - Multichannel prioritizer - Google Patents

Description

The invention relates to automation and computing and can be used in priority devices to control the maintenance of applications. The purpose of the invention is to expand the functionality of the device by

ensuring the possibility of servicing extraordinary requests. The device contains encoders, switches, elements NOT. AND, INE, OR, switches, comparison circuits, priority node, descrambler, counters, triggers. The device decides the alternate operation of up to 7 cycles, one quantum of each request. In this case, the counting of quanta is provided by counters, a group of comparison circuits and a group of switches carry out the alternate inclusion of requests. When the contact of the switch of a specific channel is opened, the group of comparison circuits and the group of switches perform the extraordinary activation of the request for this channel as many times as necessary to complete it. 1 il.

The invention relates to automation and computing, namely, to priority devices, designed to control the service applications and is an improvement on the device author. St. No. 1417001.

The aim of the invention is to expand the functionality of the device by providing the ability to service special requests.

The drawing shows a block diagram of the device.

 The device contains encoders 1. switches 2, elements NOT 3, elements AND 4, counters 5, groups of elements AND-NOT 6. comparison scheme 7, switches 8. switch 9, priority node 10. decoder 11, AND-NOT element 12. triggers 13, direct outputs 14 of the flip-flops 13. output 15 of the element IS-NOT 12. the outputs 16 of the decoder 11, the signal inputs 17 of the device, the request inputs 18 of the device, the group of outputs 19 of the device, the group of elements OR 20, switches 21, the element HE 22.

The device works as follows.

Consider the operation of the device in the normal mode, that is, when there is no need for servicing extraordinary requests and the switches 21 are turned off. Requests for interruption are received on single inputs of the trigger 13 on inputs 18. Consider the operation of the device while receiving requests, for example, on the inputs 18g and 18z of the trigger 13g and 13z. At the same time, the elements of AND-NOT 61 groups are blocked by the element NOT 3ι and the code 111 is set at their outputs. In the absence of a request for the first channel, the counter 51 at the reset input is in the state "0", the encoder is b

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with a single signal at the input, it forms 111 code at the input input. Similar elements, from the 4th and all following channels, have identical signals with the first channel. The zero state of the inverse flip-flop output 1Zg through the element NOT Zg unlocks the elements AND-NOT bg of the group; the disabled state of the switches 21 unlocks groups of elements OR 20. At the outputs of the element AND-NOT 62, a code 000 is set, a signal is taken from the reset input of counter 5g, and the encoder 12, when the signal is zero, outputs the code 010 to the input of the switch 2ι. The third channel copiers have signals similar to those of the second channel, with the exception of encoder 1, which, when the input signal is zero, sends 011 to the input of switch 2.

Comparison circuit 7 compares the code from elements 6, i.e., the code lower in the direction number, which for each comparison scheme is denoted by the symbol B, with the code from the elements 62 senior in the direction number, which for each comparison circuit is denoted by the symbol A. and, as a result, produces a signal B> A.

Since the other channels function in the same way, the code 000 arrives at the input of the EE 12 element, which corresponds to the formation of a "1" signal at its output. The switch 2 of the penultimate channel sends to the input of switch 9 a code 010, and the comparison circuit 7 outputs to the control input of switch 9 a signal that there is no equality of codes, through which switch 9 issues signals to the computer on outputs 19 and to the input of decoder 11 the code received from switch 2 . e. 010. In this case, the decoder 11 generates a single signal at the output 162. which unlocks the element 4g. Having received the interrupt code at outputs 19, the computer includes a task corresponding to this interruption code. After a quantum of this task has been worked out, the computer control device generates a signal through input 17, which, through element 4g, if there is no blocking potential at input 15 at one of its inputs, as well as the presence of resolving potential of the decoder 11, subtracts from the content of counter 5g and also a signal for resetting an application of a fulfilled quantum of the problem, which sets the trigger 13g to the zero state in the absence of “1” at the input Ί82, i.e., a signal to continue solving the problem.

Thus, after solving the problem quantum, from the output of the counter 5g to the second inputs of the AND-NOT elements 62, the code 110 is received and, accordingly, the code 001 comes to its output. After the comparison circuit 7 compares the codes 111c of the element 61, 001 from the element 62. 000c of the element 6z and 111 from the remaining elements 6 at the input of the element AND-NOT 12 will be code 000, and, at the input of switch 9, from switch 2 of the last but one channel, code 011 arrives, which, when there is no code equality signal from circuit 7, compares to the computer and input to decoder 11 which is on the bus 163 and, respectively, at the input of the element AND 4 s generates a resolving potential, after which, after a computer has been working on a quantum of a problem of a given request, through element I 4z subtracts from the content of counter 5z a unit quantum of problem solution and generates a reset signal, similar to the previous channel.

After working out the required number for a particular case, the application of quanta for solving problems of each request, the codes from the outputs of the 5g and 5z counters are equal to 000, and from the outputs of the corresponding elements 6 11 1 arrive, which leads to the formation by the circuit 7 of a comparison signal of the equality of codes and the appearance of the I- element at the input NOT 12 code 111, which forms at its output 15 "0". The control of all counters at the input "-1" through the elements of AND 4 is blocked.

The switch 9, in the presence of a code equality control signal, issues to the computer a higher-priority interrupt request number from the priority interrupt block 10, which repeats the code of the highest interrupt request after the computer has processed the next quantum of problem solution for this channel until the entire task has been completed in the absence of requests for channels not working at this moment. In the case of a request for any of the inactive channels, the signal from trigger 13 through the encoder 1 generates a channel code at the input of switch 2, and also removes the reset from the reset input of counter 5 and NOT 3 unlocks the AND-NOT 6 elements, resulting in From the output of the elements AND-NOT 6, the code 000 arrives at the inputs of the comparison circuit 7 and the switch 8. The comparison circuit 7, as a result of the comparison of the 111 codes at input B and 000 at input A, generates a signal from which, through the switch 8, the output of the IEE 12 element is removed zero signal. Switch 2 issues to the input of switch 9 a channel code that is issued to the computer and to the input of the decoder 11. The latter unlocks

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the input "-1" of counter 5 through the element AND 4. Since the codes from the elements AND-NOT 6 of the working channels are 111, and the code from the element IS-NOT 6 of this channel is less than the code 111, the request of this channel is processed until the code from the element AND-NOT 6 becomes equal to 111. Then the priority scheme automatically switches to the second mode (the second type of priority).

In the case of the arrival of the application through the channel, when the channels currently operating have completed the number of quanta less than necessary, the proposed device organizes the exchange with a computer via this channel continuously. Next, requests from the working channels are processed sequentially, one quantum for each channel.

Consider the operation of the device in the mode of extraordinary service applications. It should be borne in mind that at a given time only one request can be served out of turn. When you turn on any of the switches 21, the other one, previously turned on, is automatically turned off, the switches have normally closed contacts.

For example, there is a need for an extraordinary service of an application received via the second channel to the request input 18. At the same time, an application also arrives and via the third channel to the input 18z. At the time of receipt of applications for the inverse output of the 13ι trigger - "1", 132 - ”0”, 13h “O”. The operation of the device begins as described above in the mode of the next service of requests.

For an extraordinary service application on the second channel switch 21 is turned on ₂ . At the same time, the group of elements OR 20g is blocked at the second input and the code 111 will be received at its output, which will go to the first inputs of the group of elements AND - NOT 6d.

To the second inputs of these elements through the element NOT Zg from the zero output of the trigger 13g enters "1". As a result,

the output of the group of elements AND-NOT 6 formed the code LLC. In this case, the circuit switches to the first priority level mode. In this mode, the 5g and 5z counters summarize the number of quanta worked, so the output of the group of elements AND-NOT 6h will be code greater than zero, and the output of the group of elements AND-NE 62 will be LLC code, since its second input will be "1 ”From the element NOT Zg, and the code 111c of the blocked group of elements OR 20g. Since the code from the group of elements I-NE 6z is greater than the code from the group of elements I-NE 62 and the device is in the first priority level mode, the existing request processing circuit will provide continuous testing applications with a smaller code at the exit of the ale group ntov I-NE 62. i.e. applications in the second direction until they are completely processed. After completion of the application processing in this direction, the trigger 13g is set to "0" and the 111 output is generated at the output of the I-NE 62 element group. according to the described algorithm.

Claims (1)

Claim Multichannel priority device on aut. St. No. 1417001, different in that. that, in order to expand the functionality of the device by providing the possibility of servicing extraordinary requests, the device additionally contains in each channel a group of OR elements and a switch, the movable contact of which is connected to the inverse output of the trigger, the fixed contact of the switch is connected to the first inputs of the OR elements of the corresponding channel, the second the inputs of which are connected to the inverse outputs of the counter, the outputs of the elements OR of the group are connected to the first inputs of the elements of the NAND group of their channel, fixed contacts of the switches are connected to the input of the logical unit of the device. 1660002