SU670937A1 - Multiprocessor computing system - Google Patents

Description

one

The invention relates to computing, in part, to the design of multiprogram, multiprocessor systems.

A multiprocessing computing system 1 is known that contains interconnected processors, an interrupt control unit and a random access memory (RAM), each processor including a RAM interfacing unit, an operating unit, a control and synchronization unit, a current priority register, and a comparison circuit. and control unit.

The disadvantage of this system is the large amount of time it takes to switch tasks.

Of the known multiprocessor computing systems, the closest in technical essence to the invention is multiprocessor computing system 2. It contains processors, interrupt control device and random access memory, the inputs and outputs of which are connected respectively to the first output and input of each nz processors, the second output of each processors connected to the corresponding inputs of other processors, each of the processors contains a mating block, the first input and output of which sootvetstvelo connected with nerve input and output processor unit performing operatsny, a first output connected to the second input interface unit, the second output of which is connected to the first input of the block operations, a second output connected to the input control block. The output of the control unit is connected to the first input of the control unit and

synchronization, the first output of which is connected with the second input of the operation execution unit, the third output of which is connected through the first AND element and the OR element connected in series to the first

the current priority register entry. The second input of the latter is connected to the second output of the control and synchronization unit, and the output is connected to the second input of the processor, the first input of the priority comparison circuit and the first input of the comparison circuit, the output of which is connected to the second input of the control and synchronization block, the third output connected via the blocking trigger group to first entrances

the groups of elements And, the second inputs of which are connected to the corresponding inputs of the processor, and the outputs - with the inputs of the compared priorities. The output of the latter is connected to the second input of the comparison circuit,

the third input of which is connected to the second input of the processor and to the first input of the second element AND, the output of which is connected to the input of the element OR, and the second input is connected to the second input of the first element AND and the fourth output of the correlation and synchronization unit. The disadvantages of a multiprocessor computing system known are the high hardware costs of implementing the prioritized distribution of tasks among processors and the large amount of time required for switching tasks. The purpose of the invention is to simplify and increase the speed of the system. The goal is achieved by the fact that in a multiprocessor computing system the interrupt control unit contains a block of priority selection of requests, a block for setting the register of filled queues, a register of filled queues and a block for determining the highest unit, the third processor outputs are connected to the inputs of the interrupt control selector , the output connected to the input of the installation unit register of queues, the output of which is through the register filled ocher The action is connected to the input of the senior unit determining unit, the output associated with the output of the interruptor control device and the second input of each of the processors, the third output of which is connected to the first output of the input unit inserted into each processor, the second output of which is connected to the third input of the counter unit the input, with the fourth output of the operation block. The system diagram is shown in the drawing. It contains processors 1, random access memory (RAM) 2, interrupt control device 3, each of the processors includes an interface unit 4, an operation unit 5, a control and synchronization unit 6, a control unit 7, a current priority register 8, a priority comparison circuit 9, a comparison circuit 10, a queue block 11. The device 3) with interrupted shunting contains a block 12 of priority selection of requests, a block 13 for setting the register of filled queues, a register 14 for filled queues, a block 15 for determining the highest unit. The computing system also includes elements AND 16, 17, a group of elements AND 18, 19, an element OR 20, a group of trigger triggers 21, 22. The processing of information in the processor 1 is carried out by a unit 5, which exchanges information with the RAM 2 by means of an interface 4. The control and timing pulses necessary for the operation of the processor are generated by the control and timing unit 6. At the same time, its first output synchronizes the operation of block 5, the second output - changing the register 8 of the current priority, the third output - receiving information into the blocking triggers 21, 22, and the fourth output - receiving information into the register 8 of the current priority. Unit 7 controls the operation of unit 5. If there is a failure, the monitoring unit 7 transmits information about the failure to the control and synchronization unit 6, which, through the fourth output, sets the highest priority in register 8 of the current priority and transitions to the diagnostic mode to localize the fault. Multiprogram operation in this multiprocessor system is organized as follows. The operating system assigns a program priority to each program (it is possible to assign the same priority to several programs). For each of the possible priority values, the operating system creates a queue of programs. In this case, part of the queues may be empty if there are currently no applications for executing programs with these priorities in the system. The distribution of programs on the processors occurs with the help of the interrupt control device 3. The program enters the queue by the processor 1 by transferring information from block 5 through its fourth output to block 11 to enter the queue, which sends the program information to RAM 2 via the second output, and the request and priority number of the program to the third output of the processor via the second output 1, which is connected to the input of block 12. Block 12, the priority selection of requests while simultaneously addressing it to multiple processors 1, selects the highest priority (by positional priority) and sends the priority number of the program to block 13 setting the register of filled queues, which sets in "1 the corresponding bit in register 14. Thus, as the operating system enters the program in a queue of different priorities in register 14, units are set in the bits corresponding to the priorities of non-empty queues. The unit 15 for determining the senior unit generates at the output a binary code of the highest priority non-empty queue. When executing the current program on processor 1, block 5, through schemes AND 17, OR 20, enters the priority of the program being executed in register 8 of the current priority. The equipment of the processors continuously compares the priorities of the programs being executed in all processors to the processor whose program has the lowest priority becomes a candidate for interruption. This processor is case sensitive.

14 checks whether there is a program in the queue with a priority higher than that which it executes. If there is such a program, the interrupt candidate processor interrupts the execution of the current program, puts it in the queue list and selects the program with the highest priority from the list for execution.

The equipment operates as follows.

In each processor, circuit 9 compares the current priorities of this and other processors and generates a single signal at the output if the current priority of this processor is less than the current priorities of other processors. The group of elements 18, 19, controlled by the blocking triggers 21, 22, is used to disconnect from the circuit 9 the comparison of priorities of processors that do not participate in the operation (for example, processors that have a failure or are under prevention). The blocking triggers are installed by the operating system via the third output of the control and synchronization unit 6.

If there is a unit at the output of the priority comparison circuit 9, the circuit 10 is included which compares the contents of the current priority register 8 with the output of the block

15 determine the highest unit of the interrupt control device 3. If the contents of the current priority register are less than the code at the output of the senior unit, then this means that in the queue list there is a program with a priority higher than the program executed by this processor.

In this case, the output signal from the comparison circuit 10 is fed to the second input of the control and synchronization unit 6, which, through block 5 and block I, enters the current program into the queue, and through the interface 4, selects from the RAM 2 tasks from the queue with priority corresponding to the code at the output of block 15 for determining the highest unit. If the last program is selected from the queue of this priority, then block 5 through blocks 11, 12 and 13 extinguishes the corresponding register bit 14.

Thus, the interrupt control unit 3 performs the distribution of programs among the processors 1, choosing from the program queues the highest priority.

Introduction of the register 14 of the filled queues and the senior unit 15 to the interrupt control device 3 allows to continuously compare the priorities of the tasks solved on the processors 1 and the tasks assigned to the priority queues. This reduces task switching times and improves system performance.

Claims (2)

1. US Patent No. 3533082, cl. 340-172.5, published. 1970. 2. US patent number 3421150, class. 340-172.5, published. 1969.