SU1259278A1 - Interface for linking processors in multiprocessor computer system with variable configuration - Google Patents

Abstract

The invention relates to computing, in particular, to multiprocessor, multiprocessor systems operating in real time. The purpose of the invention is to increase the reliability and survivability of the system by eliminating the situation in which the system ceases to respond to the receipt of a service charge when the interrupt candidate processors fail. In addition, timers, interrupt request register, fault register, counter of non-served, first and second AND groups of elements, and OR element are introduced into the processor interface. If the application for executing a program has not been served in the allowed time, it is considered unserved. The unserved servicing counter accumulates the number of unattended requisitions and when the threshold level is exceeded (the admissible amount of unsuccessful servicing), a processor malfunction signal is generated, which, like a higher priority, goes to other process interface devices on non-registered registers. serviceability. Processors through the processor configuration registers and memory device configuration registers configure the computing system for this situation. In the case of failure of any candidate processor for interruption, the system can automatically reconfigure the system through processor interface devices in a time that does not exceed the allowable real-time control service (channel), and thus exclude the faulty processor from Procedures for selecting an interrupt candidate processor. 2 silt with (L ate

Description

I

The invention relates to computing and, in particular, to the design of multiprogram, multiprocessor systems operating in real time.

The purpose of the invention is to increase the reliability and survivability of the system.

FIG. Figure 1 shows a block diagram of a multiprocessor computing system with variable configuration; in fig. 2 shows an embodiment of a memory device.

The system contains processor interfacing devices 1, memory devices 2 and processors 3, Processor interface 1 contains a processor configuration register 4, a processor position number register 5, a current priority register 6, a program queue filling register 7, a high priority selection node 8, a block 9 for interfacing with memory devices and a block 10 for interrupting a processor. The interfacing unit 9 with the memory devices contains a group of 11 elements AND, a group of comparison circuits 12 and the element OR 13. The processor resolution resolution unit 10 contains the groups 14 and 15 elements AND, the low priority selection section 16, the low number selection section 17, circuits 18 and 19 comparisons and the element OR 20.

In addition, device 1 contains a program synchronization unit 21 containing timers 22, a register 23 for a wok for interruption, a register 24 for faults, a counter 25 for unserved services for, a first and second groups 26 and 27 And elements, an OR element 28, And 29 elements, and also, the interrupt enable bus 30, the interrupt bus 3, the interrupt vector bus 32 and the setting of the register bits of the request and the fault register to the initial state.

The program synchronization unit 21 contains timers 22 according to the number of control channels serviced. Each control channel is assigned a frequency, which is the empty subscriber period for the given channel in real time, T1, where n, and n is the number of control channels. As timers, counters with a fixed or variable counting coefficient are used predominantly, for example, IC K155IE7, with the support 25

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A common frequency for program synchronization blocks are signals of a single-time service, for example, from a quartz oscillator of a synchronization unit of the entire system (complex) of control.

- Counter 25 of unserved requests contains a counter with a fixed or variable counting coefficient,

The 10 defining threshold condition is the permissible number of accumulations of gx signals, in this case the number of unserved requests. Memory device 2 contains nodes the same as

15 and a storage unit 34, a sample control unit 35, a configuration register 36, and a interface unit 37 with: processors. In addition, a multiprocessing computing system

20 (Fig. 0) contains a privileged mode bus 38, a processor information bus 39, an information device. Pin 40 of the memory device, a processor fault bus 41, and a faulty processor shutdown bus 42. Processor interface block 37 (FIG. 2) contains a register 3 position number of memory device 2, register 44 logical number

30 memory devices, first and second priority switches 45 and 46, unit 47 system operations, circuits 48 and 49 comparisons, groups 50 and 51 of elements And, and a group of 52 elements

35 NOT. Each processor interface has a register 5 of the position number of the processor, which is set constant for the given computing system. All processors have different positional numbers. The configuration of the multiprocessor computing system is determined by the contents of the register 4 of the processor and register 36 of the configuration of the memory device. If all bits of these registers are set to position 1, then the system forms a single complex, which includes all processors

50 3 and all 2 memory devices.

System communication between processors and memory devices for exchange. The information is as follows.

55 The processor 3 excites, on information buses 39, the address of the memory cell being accessed and the information that is needed.

Dimo write to the specified address in the case of a write operation, as well as the position number from the register 5 of the position number of the processor. At the same time, there is no signal on bus 38 of the privileged mode. The processor interface 37 with the processor, depending on how many processors the memory device 2 is accessing, switches to its output either the information of one processor or the information on the position priority number of the processor.

The sampling control unit 35 calls the memory unit 34 at the received address and switches the position number of the processor from the output of the processor interface 37 to the information bus 40 of the memory device. The signals from the information buses 40 of the memory device pass through a group of 11 elements AND of the processor interface 1 and arrive at the inputs of the comparison circuits 12, where they are compared with the contents of the register 5 of the position number of the processor. Coincidence of numbers means 4to device 2 of memory received a request for access from this processor and proceeded to perform the operation specified by the processor. In this case, in the case of a write operation, the comparison circuit 12, via the OR element 13, outputs a signal to the processor 3, which fixes the end of the communication session of the processor with the memory device 2. During the read operation, the memory device 2 drives on the information buses 40 of the memory device 2, in addition to the position number of the processor, also read information from the indicated cell of the storage unit 34. The comparison circuit, via the OR 13 element, commutes information from the information bus 40 of the memory device 2 to the processor 3 which, according to one of the information fields 39, signals to the memory device 2 the end of the communication signal.

Memory configuration register 36 serves to disconnect processor memory 2 from the device. The setting of the register 36 of the memory configuration is performed by the processor 3. At the same time, the latter generates a signal on the bus 38 of the privileged mode, Block 37 of the processor interface

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 compares the position number of the memory device 2 with the higher address bits and, where these numbers coincide, transmit information to the 5th input of the block 36, in the case of accessing several processors, the block 37 joins the processor to its output from one of the inputs for position prioritize 10 tu.

In the embodiment of the memory device 2 shown in FIG. 2, the work is as follows. Each memory device has

15, the register 43 of the position number of the memory device, which in each memory device 2 is set constant for the given computing system. All memory devices 2 have different positional numbers. Each memory device 2 has a register 44 of the logical number of the memory device, the contents of which determine to which device 2 the processor's address is addressed. When reading (writing), there is no signal on the bus 38 of the privileged mode, and the outputs of the group 52 are NOT elements 2 memory devices

have the value 1. Signals from the information bus 39 pass through a group of 51 elements AND of all memory devices and fall into the inputs of the comparison circuits 49, which

compare the high-order bits of the address with the contents of the register 44 of the logical memory number and, in the event of a match, commute the input information to the input of the second priority

commander 46. The second priority switch 46 in the case of simultaneous access to one device 2 memory of several processors selects and switches its output

information from one of the inputs on the positional priority. The position number of the processor from the corresponding bits is output from the output of the second priority switch 46.

The setting of the register 36 of the memory configuration is as follows.

The processor generates a signal on the privileged mode bus 38, and in the memory device 2, the corresponding groups of 50 elements AND are opened, and groups of 52 elements do NOT close the group of 51 elements I.

. . five

The position number in the position number register 43 is compared with the higher address bits, which, through a group of 50 elements, arrive at the input of the comparison circuits 48. In the device 2 of the memory where these numbers match, the comparison circuit 48 transmits information to the input of the priority switch 45, which, in case of simultaneous access of several processors, selects and switches to its output information from one of the inputs by positional priority. The system operation block 47, in accordance with the received information, controls the setting of the memory configuration register 36 and the register 44 of the logical number of the memory device, and

Multiprogram operation in this multiprocessor system is organized as follows.

It is assumed that the system performs n real-time maintenance programs corresponding to n control channels (objects), the Operator system at each stage of the logical-temporal diagram of work assigns the corresponding set of programs to be executed by the system, generates a program set code and writes it into a fixed cell memory Each bit of the cell corresponds to one of the n programs. The unit per bit is the condition for including this program in the set, i.e. a sign of its installation in the program queue, zero in the discharge - a sign of the absence of this program in the set. The code of the set of programs is rewritten from the memory cell to .register 7 of the software queues of the processors and enters the hardware of the interface and implements the queue of requests for the execution of the programs. The check register 23 forms a queue of requests for this processor, and if the queue receives a request for executing a program of higher priority than the current priority of the program executed by the processor, and the processor interrupter resolution block 10 generates a processor interrupt enable signal, the processor hardware produces interrupt the current program, put it in a queue and start to execute a higher priority program.

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If the application for the execution of the program was not served within the allowable time, then the application is considered unserved. The counter 25 of the unworked orders produces an accumulation of unattended requests and by exceeding the threshold condition (the allowable number of unattended requests) produces a signal Failure of the processor, which arrives as a higher priority for other processors in the fault register 24, and the processors, through the configuration registers 4 of the processors 15 and the memory device configuration registers 36, reconfigure the computing system for this situation. The equipment is working; melts as follows.

20 Processor 3 selects from device. 2 memories in the program queue register 7, the contents of the fixed cell storing the program set code. The information from register 25 through the first group 26 of the elements I enters register 23 for interrupt, at which time the arrival at the corresponding register register 23 for synchronization is synchronized with signals from the corresponding timer 22 of the program synchronization block 21. Upon receipt of the application in register 23, node 8 of the choice of the highest priority compares the priority of the received application with the priorities of previously received and not yet served requests. If the priority of a submission is lower than those in the system, then the application is remembered in

0 register 23 for interrupt and and "is queued. If the priority of the incoming application is in the system, then the high-number selection node 8 generates an interrupt signal, which through element 29 and the interrupt bus 31 enters the processor 3 if the interrupt enable unit 10 generates a signal on the interrupt resolution bus 30 .

The formation of the pregloan resolution signal on the resolution bus 30, the preregoan in the considered multiprocessor computing system, is performed as follows.

When executing the current program, processor 3 puts its priority in

-. one

register 6 of the current priority. Information from the current priority register of each processor enters through a group of 15 elements; And to node 16 for selecting priority of d {ear processors. In each processor, node 16 for selecting lower priority compares the current priorities of other processors and commutes to its output the code of the youngest of the compared current priorities. In case of equality of the textual priority codes at the inputs of the selection node 16, the code is switched to its output by comparing the current priorities. The code from the output of the selection unit 16 is fed to the input of the comparison circuit 19 (priorities) for comparison with the contents of register 6 of the current priority of a given process. If the contents of this register of the current priority of this processor is less than the code generated by the junior priority selection node 16, this processor performs the task with the lowest priority and becomes a candidate for an interrupt. In this case, the comparison circuit 19 is outputted at its second output: a signal which, through the OR element 20, arrives at the output of the interrupt resolution unit 10. If the contents of register 6 of the current priority of a given processor are greater than the code generated by selection unit 16, then this processor is not a candidate for an interrupt, and the first and second outputs of comparison circuit 19 are zero.

If the contents of register 6 of the current priority is equal to the code of the younger current priority, then this means that two or more processors execute programs of the same priority. In this case, the interrupt candidate processor is selected by the lower position number by the junior selection nodes 17 and the comparison circuits 18, operating similarly to the selection nodes 16 and the comparison circuits 19, respectively. In this case, the signal at the second output of the comparison circuit 19 is zero, and at its first output, a signal is generated that includes the third selection node 17, to the input of which, through a group of 14 elements And, information from the outputs of the registers 5 of position numbers of other processors. Junior Position Number from Exit

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The node 17 of choice is fed to the input of the comparison circuit 18, where it compares with the contents of the register 5 of the position number of this processor. 5 If the contents of register 5 of the position number of the processor are less than the code of the lower position number, then the comparison circuit 18 generates a signal which, through the OR element 20 10, arrives at the output of the interrupt enable unit 10.

The current priority register 6 contains 1 + n bits, where the first (senior) bit corresponds to the fault signal of this processor and is set to one if on the bus 32 disconnecting the faulty processor the output signal is received, the other bits of 20 correspond to h executable programs, i.e. currently, only one of the bits can be set to state 1, with the discharge measure yogi specifying the number of the current priority. If a signal is generated on bus 32, then all n bits of register 6 of this processor are set to zero. In this case, comparison circuit 19 is given 1 + n bits of register 6,

and the second inputs of groups 15 elements And other processors receive bits from register 6 of the current priority of this processor, 35 Processor 3 when a signal is received An interrupt on bus 3 interrupts the execution of the current program by this processor 3 and proceeds to the execution of programs of the operating system. At the same time, processor 3 — the code of the program being interrupted from the block 8 for selecting the higher number via the bus 32 of the vector of the interruption — writes it into a fixed cell, compares the code of the program being interrupted with the code of the program set executed by other processors of the system at the moment. If this program is already being executed by one of the processors, then 5 (j operation block via bus 33 sets the corresponding register to the initial state to the initial register and writes off this program from the program queue to 5J to this processor.

If this program is not executed by any of the system processors, then the operating unit is

accomplished

the course of the program proceeds to the prejudiced program.

Upon completion of the program execution, processor 3 via bus 33 sets to the register 23 of the application corresponding to the program, the bit to its original state, while all other bits of the register 23 remain unchanged, i.e. This program is removed from the program queue until the next program enters it.

If this program did not execute within the allowable time, then the next signal from the timer 22 corresponding to this program goes through the corresponding element AND of the first group of 26 elements AND to the second input of the corresponding element AND of the second group 27 elements AND, to the first input of which enters at the given moment a single signal from the corresponding to this program, register register 23 order, since the signal about the end of this program is not received. At the same time, from the output of the corresponding element of the given program And the second group of 27 elements, through the element OR 28, a signal arrives at the input of the counter of the unserved 35.

When exceeding the threshold, i.e. on the first output, the signal that goes to other processors through the bus 41 faults. processor, and at the second output, a signal is generated, which is fed to the second input of the register 6 of the current priority through Tina 42 disconnecting the faulty processor.

In this case, the current priority register 6 is set to the state corresponding to code 100, .. O, and through its own comparison circuit 19 and nodes 16 the selection of the younger priority of other processors is automatically excluded from the processor selection procedure candidate for interruption. The signal due to 4 processor malfunctions is fed to the corresponding input of the input group of the register 24 of malfunctions of other processors. The information from the fault register goes to the corresponding input of the group into the input of block 8 for selecting the highest number as

ten

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0

five

0

five

0

five

0

45

a higher priority than any application received from register 23, a request, i.e., a processor (if there is a signal for 30 times to solve the processor), interrupts the execution of the current program and proceeds to run the system reconfiguration program this situation. Upon completion of the reconfiguration program, processor 3 selects the termination code of this program from the memory and, via bus 33, sets it to fault register 24, while the corresponding register bit 24 is set to the zero state, and all other bits 24 and register 23 remain unchanged, i.e. service program for a signal by request The malfunction of another processor is removed from the program queue of this processor.

The system configuration change is controlled by the processor configuration registers 4 and the memory configuration registers 36. Setting the register 4 of the processor configuration is done by the processor 3. Part of the bits of the register 4 of the processor configuration serves to disconnect from the processors of the memory device 2. This shutdown is performed by locking the group of 11 elements I.

Another part of the register 4 bits of the processor configuration serves to exclude the processors 3 from multiprogram operation. In this case, a group of 14 I elements serves as the dp of excluding a disconnected processor from the procedure for comparing positional numbers, a group of 15 I elements for excluding the comparison of current priorities from the procedure. I

50

The application of the proposed elements and communications that implement the procedure of forming queues of requests for executing programs in separate processors in real time, allows for the failure of any processor to automatically reconfigure the system through other processors. In a time that does not exceed the allowable value for servicing channels (objects) up 55 in real time and thereby exclude the faulty processor from the procedure for selecting a candidate processor for interruption.

and

Claims (1)

Invention Formula A processor interfacing device in a multiprocessor computer system with a variable configuration, containing registers of the system configuration, the position number of the processor, the current priority of the task, and the filling of program numbers. Redey, interface blocks with memory devices and interrupt resolution of the processor, high priority selection node and AND element, the interface block with memory devices contains the OR element, the group of comparison circuits and the key group, and the processor interrupt resolution block contains the OR element two comparison schemes, a junior number selection node, a junior priority selection node and two groups of keys, the installation input of the position number of the device processor is connected to the information input of the position number register of the processor, the output Expensive is the output of the processor number in the system of the device and is connected to the first information inputs of the comparison circuits of the interface unit with the memory devices and to the first input of the first comparison circuit of the processor interruption gap block, the input of the installation of the current priority of the device task is connected to the information input of the current register the task priority of the device and is connected to the first information input of the second comparison circuit of the processor interrupt resolution block, the input of the device system configuration setting connected to the information input of the system configuration register, the first group of outputs of which is connected to the control inputs of the keys of the interface unit with memory devices, the second group of outputs of the system configuration register are connected to the controls of the inputs of the keys, the first and second groups of the processor interrupt enabler, The group of processor number inputs in the system and the group of inputs of the current priority of the device are connected to the information inputs of the keys of the first and second groups; the interrupt processor resolution block corresponds to These outputs are connected to the information inputs of the junior number selection nodes and Vy5927812 the junior priority boron, respectively, and the outputs of these nodes are connected to the second information inputs of the first and second comparison circuits of the processor interrupt resolution block 5, respectively, whose outputs are connected to the first and second inputs of the OR interrupt processor resolution block, a group of information inputs the device is connected to the information inputs of the keys of the interface block with the memory devices, the outputs of which are connected to the second information inputs of the corresponding 15 comparison circuits of the interface block with memory devices, the outputs of which are connected to the inputs of the OR element of this block, and its output is the information output 20 of the device, the installation input setting of the software queues of the device is connected to the information input of the filling register, software queues, the output of the interruption request 25 output item. And, the first input of which is connected to the output of the tracking of the senior priority selection node, which is due to the fact that, in order to ensure the reliability and survivability of the system, a group of timers was entered into the device; interrupts and malfunctions, the counter of unattended orders, the first and second groups of AND elements and the OR element, while the timer outputs are connected to the first inputs of the corresponding AND elements of the first group, the second inputs of which are connected to the outputs of the corresponding 0 register bits filling in software In the first group, the outputs of the elements of the first group are connected to the information inputs of the register of the interrupt request and to the first inputs of the corresponding elements AND of the second group, the outputs of the register of the interrupt request are connected to the second inputs of the corresponding elements of the second group and to the information inputs the node of choice 0 of the highest priority, the output of the interrupt vector of which is the same output of the device, the outputs of the elements AND of the second group are connected to the inputs of the OR element, the output of which is connected to the counting input of the counter tinned requisition, clock inputs of the fault register and interrupt wok soe13 dinene with a device sync input, the output of the register of the faulty tey is connected to the information inputs of the high priority selection node, the output of the processor shutdown resolution block is connected to the second input of the And element, the first output of the unmanaged meter is connected to 12592781 the lock input register of the current priority of the task; the second output is the symptom output of the fault. device, with inputs 5 signs of device malfunction. connected to the information inputs of the fault register.