SU923015A2 - Pulse repetition frequency multiplier - Google Patents

Description

(54) MULTIPLE OF FREQUENCY FOLLOWING PULSES

I

The invention relates to a pulse technique and can be used in systems for processing and transmitting frequency information in sound synthesizers.

According to the main author. St. N 657598 a pulse frequency multiplier is known which contains a serially connected code register, an installation unit, a pulse counter, a code converter, a voltage, and a comparison unit, the second input of which is connected to the output of the sawtooth generator, and the output is connected to the pulse counter input , a delay unit, the output of which is connected to the input of the sawtooth generator, a dynamic memory and a pulse generator, the input of the dynamic device being connected to the output of the saw generators shaped voltage, and the output - to the input of a code-converter voltage; the input of the pulse voltage generator is connected to the input of the delay unit, its first output is connected to the input of the pulse counter, the second f is connected to the input of the dynamic zap (1 MHz device, and the current is connected to the second input of the sawtooth voltage generator.

Formation multiplied by 2, where, 2.. . , the sequence is carried out at equal voltages from the output of the sawtooth voltage generator and the output of the code-voltage converter. In this case, the output voltage of the code-voltage converter depends on the number of pulses counted by the counter, the weight of the low-order bit,

10 depending on the multiplication factor and the magnitude of the reference voltage, set dynamically by the memory device and changing as the output pulse frequency changes.

five

A disadvantage of the known device is to obtain a limited range of multiplication factors of 1.

The purpose of the invention is to obtain an arbitrary multiplication factor.

20

The goal is achieved by introducing a control unit into the pulse frequency multiplier, the KOTOpoiO inputs are connected to the code register inputs, and a variable attenuator, the input of which is connected to the output of the sawtooth generator, the control input with the output of the control unit, and the output . with the input of the comparison block. FIG. Figure 1 shows a structural electrical circuit of a pulse frequency multiplier; in fig. 2 time diagrams for his work. The pulse frequency multiplier contains a delay unit 1, a generator 2, a sawtooth voltage, an adjustable attenuator 3, a comparison unit 4, a pulse generator 5, a dynamic memory 6, a code-voltage converter 7, an attenuator control unit 8 and a pulse counter 9 , multiplication factor register 10, the setting unit AND the pulse counter. The device works as follows. The impulses of the input sequence (Fig. 2a), when passing through the delay unit, are delayed by a small constant value (Fig. 26), which is necessary for the correct operation of the nodes of the proposed device, and then start the sawtooth generator 2, which forms a constant saw slope and constant operation at constant frequency or variable duration at a slowly varying input frequency (voltage UUH in Fig. 2e). The voltage of the saw before the moment of reset of the generator 2 is fixed for the subsequent period by a dynamic storage device 6 (Fig. 2e) and serves as a reference voltage for the converter 7 code voltage. The multiplication factor, 1de p 0.1, K; .Р is a simple or compound odd multiplier, is recorded in the binary code and registry of the IO code and through the setting unit 11 sets the weight of the lower bit of the counter 9 pulses equal to 2. With a day grid of the counter of the counter 9 pulses of 2 square bits and, accordingly, the same number of bits in the code-voltage converter 7, in the proposed device it is possible to obtain multiplication factors by more than 2. At the same time simple or compound odd multiplier P 2. The arrival at the input of the counter 9 of the next pulse from the comparison unit 4 causes the output of the converter 7 code voltage, the value of which is directly proportional to the weight 2 of the lower bit of the counter 9, the hook and the value of the next with the code-voltage converter 7 This voltage increment is summed with the voltage level} 1i that the code-voltage converter 7 has generated at the arrival of all the preceding ones. pulses within one period of the input frequency (voltage of the CPC in Fig. 2d). The comparison unit generates 4 pulses of the output sequence (Fig. 2g), which are fed to the clock input of the pulse counter 9, when the equality between the weakened adjustable attenuator 3 of the sawtooth voltage (voltage Uam) coming from the sawtooth generator 2 and the voltage generated by the code-voltage converter 7. The attenuation factor, controlled by attenuator 3, is constant for each multiplication factor, but varies with the attenuator control unit 8 depending on the multiplication factor for the purpose of the equation at the end of the voltage period at the inputs of the comparison circuit 4. This is necessary due to incomplete filling the counter in the presence of the magnitude of the multiplication factor of a simple or compound odd multiplier P and, accordingly, the formation at the output of the converter 7, the voltage code voltage less than the maximum level . In the absence of an odd simple or compound multiplier P, the transmission coefficient of the adjustable attenuator 3 is equal to 1; in the presence of such a multiplier, it is equal to p. the 2P 2, Broadband operation of the device is ensured by simultaneously changing the duration of the sawtooth voltage and the magnitude of the step from the code-voltage converter 7, which is associated with a parallel voltage change at the output of the dynamic storage device 5, which is the reference voltage for the hydrogen generator 7 codepower. For the correct operation of the proposed device, a pulse generator 5 is used, which is synchronized by the input frequency and produces: control operation of the dynamic storage device 6, a pulse sequence ensuring fixation at the end of the operation cycle of the generator 2 sawtooth voltage of the output voltage 6 ( Fig. 2c), a delayed control impulse sequence that, at the end of the work cycle, resets the generator 2 of the saw-tooth voltage and provides a reset Leniye s1etchika 8 pulses. The use of additional nodes and links, which are absent in the known device, allows an arbitrary pulse frequency to be obtained in the proposed multiplier.

multiplication coefficient, which makes it possible to use the device more widely.

Claims (1)

Invention Formula Pulse frequency multiplier by aut. St. No. 657598, characterized in that, in order to expand its functionality, a control unit is inserted in it, the inputs of which are connected to the inputs of the progress register, and an adjustable attenuator, the input of which is connected to the output of the saw-tooth generator, the control input with the output of the control unit, and the output is with the input of the comparison block.