SU922712A1 - Information processing device - Google Patents

Description

 The invention relates to computing technology, in particular to complex digital systems, information processing (ITN) with a variety of input / output devices.

Creating an effective SOI leads to an increase in the number of devices connected to the system. However, it is not possible to increase the number of devices indefinitely because of the limited possibilities of the load capacity and the geometric length of the communication channel connecting the devices of the system.

The PIO is known, comprising a processor, a trunk communication channel, a random access memory, I / O devices 1 and 2.

The disadvantage of this system is the low speed and low load capacity of the communication channel.

The closest technical solution to the invention is an information processing system, comprising a processor, connected by a first information control bus with a random access memory, a device for input or output of the first group and with bus extenders;

The first output group output and bus extenders, group I / O devices connected to the bus extenders by the second transmission request bus, the second information control, the bus and the second unidirectional transmission resolution bus, the processor of the first unidirectional transmission resolution bus connected with I / O devices of the first group

The disadvantage of such a system is relatively low speed with an increase in the number of devices.

15 in the system, due to an increase in the exchange time between devices located on different sections of the communication channel.

The purpose of the invention is to increase the speed of the system.

This goal is achieved by the fact that the system contains serially connected peripheral arbitrators connected to the respective tire expanders, the input of the first peripheral arbiter is connected to the output of the input / output device of the first group. In addition, the peripheral arbitrator contains a block of receivers, a transmission request register, a kollutator.

two transmitter units and a synchronizer whose input is connected to the output of the receiver unit and the first input of the switch, the first output to the input of the register of transfer requests, the second output to the second input of the switch, the third input of which is connected to the output of the register of transfer requests, outputs to the inputs of the first and second block of transmitters.

Figure 1 shows the block diagram of the information processing system; figure 2 - block diagram of the peripheral arbitrator.

The information processing system contains bus extenders 1, peripheral arbitrators 2, input-output devices 3 of the first group, processor 4, random access memory 5, input-output devices b of the second group, first information control bus 7, first bus 8 request transmission, first unidirectional bus 9 enable transmission, second bus 10 Transmission requests, second information control bus 11, second unidirectional bus 12 transmission resolution, block 13 receivers synchronizer 14, register 15 transfer requests, switch 16, p The first block of .7 transmitters, the second block of 18 transmitters.

The system works as follows.

The signal source over the first unidirectional transmission resolution bus 9 is the central processor 4.,.

Consistently distributed through the I / O Devices 3 of the first group, the transmission enable signal selects only one device among the devices requiring maintenance. This signal, arriving at the input of the first device 3 of the first group, is analyzed, and in case of a request by the service device, it is entitled to use the system resources. Otherwise, the transmission enable signal is sent to the next. I / O device 3 of the first group. In this case, the consistent nature of the propagation of the indicated signal by the actual .n only within the devices of the first and second unidirectional buses 9 and 12 of the transmission resolution, respectively.

The transmission enable signals are processor counts to the transmission request signals coming from the devices 3 and b of the system on the first and second buses 8 and 10 of the transfer requests, respectively.

The processor allocates the request to the highest priority and generates a transmission enable signal. This signal passes through all the I / O devices 3 of the first group and, if there is no device among the nickname that the signal intended for, reaches the input of the first, peripheral arbiter 2, its purpose is to determine whether the device is in the receiver the transmission enable signal to the second unidirectional transmission 12.

The processor 4, in conjunction with the random access memory 5, the first and second information control buses 7 and 11, the buses 8, 10, 9 and 12, the peripheral receivers 2 and the bus extenders 1 processes the data.

Consider now the principle of operation of the peripheral arbiter 2 in accordance with figure 2.

In the initial state, there are no signals at the inputs of the block 13 receivers. Accordingly, there are no control signals at the inputs of the switch 16, and, as a result, there are no signal signals at the outputs of the first and second blocks 17 and 18 of transmitters, respectively. The state of the inputs of the peripheral arbiter 2 is indifferent.

Claims (3)

Suppose that one of the devices requires system resources, will generate a request transmission signal. This signal reaches the bus expander 1 and is transmitted last to the first bus 8 transfer requests. The Transmission Request signal, distributed on the first transmission request bus 8, reaches processor 4. Processor 4 performs arbitration (allocating a request that has the highest priority) and, if conditions allow, generates a signal and the corresponding line of the first unidirectional transmission resolution bus 9, which reaches input peripheral arbiter 2 - input unit 13 receivers. Passing through the receiver unit 13, the transmission enable signal enters the synchronizer 14 and the switch 16. As a result, the latter is adjusted in accordance with the priority of the incoming signal. A synchronizer 14, which starts every time one of the signals from the group Allows transmission, arrives to write into the register 15 requests to send requests to the input devices 6 of the second group. After some time, determined by the synchronizer 14, the last signal is generated at the control input of the switch 16, analyzes one of the triggers of the transfer request register 15 in accordance with the previous setting of the switch 16 If this trigger is set to the logical 1 state, the transfer resolution passes through the second transmitter unit 18 and then transmitted through the bus expander 1 to the second unidirectional transmission resolution bus 12. Thus, the peripheral arbiter prohibits further propagation of the signal in the first unidirectional (foam transmission resolution bus 9 and translates it into the second unidirectional transmission resolution bus 12. Assume that the signal source is the Transmission request received in: processor 4 is one of the devices b I / O of the second group connected to another BUS expander 1. In this case, at the time of writing to the register 15, the transfer requests to the corresponding line of its input information bus preserve a logical level O (no signal Transmission Request). Therefore, the corresponding trigger is set to the logical O state, in which case the Transmission Permission signal passes to the corresponding output bus line of the first transmitter unit 17. As a result, the peripheral arbitrator 2 Performs the translation of the permission sigma transmissions to bus extender 1 (Fig. 1) .The number of lines in the corresponding buses of peripheral arbitrator 2 and the register size of the 15 transfer requests is equal to the number of priority lines in the data processing system. The information processing system is characterized by higher speed, since with an increase in the number of extenders in the system, there is no increase in the coupling cycle between devices and the device identification time. As a result, it is possible to create complex systems with wide capabilities, characterized by a large number of devices and a full load of the processor and memory (i.e., high performance). In addition, the arrangement conditions of the devices in the system have been significantly improved and the possibility of arbitrary distribution of devices along the communication channel has been ensured. Claim 1. An information processing system comprising a processor connected to a first information control bus with a random access memory, first group I / O devices and bus extenders, a first request bus of the first group I / O devices and an extender buses, I / O devices of the second group, connected to bus extenders, second bus of transfer requests, second information control bus, unidirectional bus of transmission resolution, processor of the first one A guided transfer resolution bus is connected to an I / O device of the first group, characterized in that, in order to improve system performance, it contains serially connected peripheral arbitrators connected to the appropriate expansion expanders, the input of the first peripheral arbitrator is connected to the output of the I / O device first group. 2. System - according to claim 1, differing from the fact that the peripheral arbitrator contains a block of receivers, a register of transmission requests, a switch, two blocks of transmitters and a synchronizer whose input is connected to the output of the block of receivers and the first input of the switch, the first output is with the input of the transfer request register the second output - with the second input of the switch, the third input of which is connected to the output of the transfer request register, the outputs - respectively to the inputs of the first and second block of transmitters. Sources of information taken into account in the examination 1.Filin A.V., Solokhin A.A. The organization of interrupt handling in the system interface. Technical means of minivc (INEUM works). M., General tire, 1977, no. 61. 2. Technical means of mini-computer (works of INEUM). M., 1977, vol. 61. 3. Authors certificate of the USSR 526936, cl. G 0-6 F 3/00, 1976 (prototype). 13 sixteen