SU911357A1 - Multi-threshold indicator - Google Patents

Description

(54) MULTI-THIRD SIGNALIZER

The invention relates to the instrumentation engineering and can be used in signaling and tolerance control devices. A device containing input frequency converters connected to a control unit, the outputs of which are connected to the inputs And elements, through which the output of the master oscillator is connected to the inputs of counters, the outputs of which through the key blocks are connected to the input of the comparison unit with threshold settings, is known. Comparisons of the chase trigger are associated with the recorder C. The disadvantage of this device is its low speed. The closest to the invention is a device containing a control unit, a generator-guard, a threshold element, a setpoint counter c. the decoder, the setting block and the recorder 2. A disadvantage of the known devices is the low speed caused by the fact that only one threshold value of the measured parameter is monitored for one period of the input frequency, in order to control several threshold values, it is necessary to proportionally increase the monitoring time. The goal of the invented sky is to increase speed. The goal is achieved by the fact that the device containing the input signal shaper, the output of which is connected to the control unit input: the synchronization input of which is connected to the output of the master oscillator of the reference frequency and the counting input of the pulse counter, and the output register, the outputs of which bits are connected to inputs of corresponding pointers, a threshold decoder, an inverter and a buffer register are entered, the first output of the control unit is connected to the control input of the output register and the zero setting input. A pulse generator whose bit outputs are connected to the code inputs of the decoder, the gate of which is input through an inverter connected to the output of the reference frequency generator, the outputs of the decoder are connected to the inputs of the zero register setting, the input of the unit of which is connected to the second output of the control unit, and exits

connected to the output register yohds.

The drawing shows the block diagram of the device.

The device contains an input bus 1, an input signal shaper 2, a control unit 3, a master oscillator .4 a reference clock; 1, a pulse counter 5, an inverter 6, a threshold decoder 7, a buffer register 8, an output register 9, pointers 10.

The input bus 1 is connected to the input of the transmitter 2, the output of which is connected to the input of the control unit 3, the output of the master oscillator 4 is connected to the synchronizing input of the control unit 3, to the counting input of the counter 5 and through the inverter b to the gate input of the decoder 7, the outputs of the counter 5 are connected with the inputs of the decoder 7, the outputs of which are connected to the indicators 10 through the series-connected buffer register 8 and register 9, the first output of block 3. the control is connected to the installation input in O of the counter 5 and to the control input - the input of the census of information from register 8 to register 9; the second output of control unit 3 is connected to the installation input 1 of all the triggers of the buffer register 8.

The detector works as follows.

The period measurement cycle of the input frequency starts at the moment when the input edge of the input signal from the generator 2 arrives at the input of the control unit 3. At the beginning of each measurement cycle, two successive signals are generated from the outputs of the control unit 3: the first enters the installation input O of counter 5 and the census input the result of the previous measurement cycle from the buffer register 8 to the register 9, the second to the input of the installation in 1 of all the flip-flops in the buffer register 8. The synchronization of the signals of unit 3 is carried out by applying to its synchronizing the reference frequency input from the master oscillator 4. Thus, at the beginning of each measurement cycle, the counter 5 is in the zero state, the buffer register 8 is in the unit state, and the output register 9 stores the result of the previous measurement cycle.

When measuring one period of the input frequency signals from the master oscillator 4 is fed to the counting input of the counter, 5. The threshold decoder 7 is set to the states of the counter 5, corresponding to the threshold values of the monitored parameter, and has a number of outputs equal to the required number of thresholds. The state of counter 5 is decrypted upon receipt of each input reference frequency pulse. To avoid false

the operations of the decoder 7 at the time of transients occurring in the counter 5 when each input pulse is counted, the decoder 7 is gated with an inverted signal of the master oscillator supplied by the master oscillator 4 output to the gate of the inverter 6.

When the counter 5 is filled with the reference frequency pulses, its state will be first decoded but the state corresponding to the setpoint of the highest triggered threshold (i.e. the shortest input frequency period), the signal from the output of the decoder 7 will go to the setup input of the corresponding trigger buffer register 8, indicating that the input frequency has not reached this (upper) threshold. Upon further booting of the counter 5, the state corresponding to the second from above (in frequency) trigger threshold will be decrypted and so on until the end of the measurement cycle of the input frequency period, which ends with the arrival of the leading edge of the next input pulse. At this moment, the counts in counter 5 are terminated (by setting counter 0 to 5 according to the signal from the first control output of control unit 3) J The triggers of the buffer register 8, which did not receive installation signals from 0, from the outputs of the decoder 7, retain their one state and thus, the buffer register 8 reflects the picture corresponding to the achievement or non-achievement of certain threshold values of the monitored parameter.

At a low input frequency, less than the minimum threshold value, the measured period will be maximum, counter 5 will receive the maximum number of reference frequency pulses, the decoder / 7 will decipher the states corresponding to all threshold values and set all the triggers of the buffer register 8 to O . It. means that none of the threshold values of the monitored parameter is reached.

With a high input frequency (higher than the upper threshold value), the measured period will be minimal, by counter 5. the minimum number of pulses of the reference frequency will arrive, no Signal will be generated at the outputs of the decoder 7, and all the triggers of the buffer register b will save a single state. This means that the value of the monitored parameter is higher than any of the threshold values.

Claims (1)

Claim A multi-threshold signaling device containing an input signal shaper whose output is connected to the control unit input, a synchronization input (Q of which is connected to the output of the reference frequency reference oscillator and a counting input of a pulse counter, and an output register, the discharge outputs of which are connected to the inputs of the corresponding pointers, o It means that, in order to increase its speed, a threshold decoder, an inverter and a buffer register are introduced, and the first output of the control unit is connected to the control input of the output about the 20th register and the zero-pulse input of the pulse counter, the outputs of the discharges of which are connected to the code inputs of the decoder, whose gate input is connected through the inverter to the output 25 of the reference reference oscillator, the outputs of the decoder are connected to the zero-setting inputs of the buffer register, the unit setting input of which is connected to second block output 30 controls, and the outputs are connected to the inputs of the output register.