SU907813A1 - Reversible counter - Google Patents

Description

I

The invention relates to automation and computing and can be used in conveyor automation devices.

Known counter, implemented on logic elements and used for reverse counting and indication of readings 1.

The disadvantage is its complexity

A counter on ferrite-transistor elements is also known, which contains shift and restoration registers, the key element of circulation 1, cranes, and the transfer element 2j,

A disadvantage of the known device is the impossibility of the implementation of the reverse account, t, e. relatively narrow functionality.

The purpose of the invention is to expand the functionality.

The goal is achieved by the fact that in a reversible counter on ferrite-transistor elements containing two registers, the key elements of circulation and advancement 1 and the transfer element H into the high-level counter, in which the output of each element of the first register is connected in series through a decoupling diode and a write winding element 10 of the corresponding digital cell of the second register with the key element of circulation 1 in the digital cell, as well as through the decoupling diode and the writing coil of the element of the next digital

Claims (2)

1 $ cell with advance key element 1, installation bus in O is connected to the write windings of the zero digital cell element of the second register and reading of the key circulating element 1 in series, the input counting bus is connected to the windings of reading the key circulation element 1 and writing of the key advancement element 1 in the series connection, the output of the first register element of the last (senior) digital cell is connected in series through the writing winding of the transfer element 1 to the counter with A higher bit with a key element of advancement 1 and the output of the transfer element through the recording winding of the element of the zero digital cell of the first register is connected to the bus of the transfer signal 1 to the high-order counter; the corresponding digital cell of the first register with the key element of the circulation V, as well as through the decoupling diode and the record of the preceding digital circuit of the first register, with the key element of the In Fig. 1, the output of the zero-digit element of the second register is connected in series through the winding of the transfer element 1 to the low-order counter with the key element of advancement 1, and the output of this element through the recording winding of the element of the last (highest) digital cell of the second register is connected to the bus transfer signal 1 to the low-order counter, the buses of the first and fourth clock signals are connected to the write winding of the key element of circulation 1, the bus of the third clock signal is connected in series with the winding The readings of the key elements of the circulation 1, the advancement 1 and the first register, the bus of the sixth clock signal - sequentially with the windings - the reading of the key elements of the circulation 1, the advancement 1 and the second register. The drawing shows a functional diagram of the reversible counter from O to 9 o The device contains ferrite-transistor elements, 1 1 ..., forming the first register, elements, ..., forming the second register, with pairs of elements and (, and ... and, and form respectively digital cells 1, 2, ... 9, O), which have read inputs, preparation inputs and outputs of ferrite transistor elements, decoupling diodes 0, ... The device also contains the key element 5 of the circulation of pulses 1 in digital cells, key element 6 of impulse advancement 1, elements 7 of transfer 1 to the high-order counter, transfer element 8 to the low-order counter, output 9 of transfer element 7, output 10 of transfer element 8, first clock pulse bus 11, buses 12, 13, and 1 of the third, fourth, and sixth clock pulse, bus 15 input counting pulses and bus 16 are set to O, to the outputs of the elements - output buses are connected, respectively. The outputs of elements 1 1 - of the first register are connected in series through the windings of the recording of the elements of the corresponding digital cells of the second register with key element 5, as well as through the windings of the records of the elements of the next (senior) digital cells of the second register with the key. element 6, and the element through the recording element winding 7, the outputs of the second register, are connected in series through the recording windings of the elements of the corresponding digital cells of the first register with the key element 5, and also through the recording windings of the previous (lower) digital cells of the first register with the key element 6, and the element is through the recording element 8 winding. The output 9 of the element 7 is connected via the recording winding of the zero-cell element to the input of the high-order counter, and the output 10 of the element 8 through the recording element winding the longest. (senior) digital cell with the input of the low-order counter. The bus of the 11th clock signal is set accordingly: bus 11 - to the recording element winding 5, bus 12 to the serially connected windings of element readings -, 5, 6, 8, bus 13 - to the recording winding of element 5, bus 1 - to serially connected windings read elements - 5,6,7. Input pulse bus 15 is connected to serially connected windings of reading element 5 and writing element 6 A bus 16 connected to serially connected windings of writing element and reading element 5 is given a pulse to set the counter to zero. To the outputs of the elements - connected to the output bus 17-26, which can be connected, for example, with the display device. The device works as follows. The pulse of addition 1 coinciding in time with the second clock pulse is read element 5 and element 6 is being prepared. By the third clock pulse elements are read, .. ,, 5, 6 and 8. If, prior to the pulse of add 1, the counter is, for example, O, e, by the time the third clock pulse was received, an element was prepared, then elements and 6, connected in series through the element preparation winding and isolation diode 1, will prepare an element. The fourth clock pulse prepares element 5. The sixth clock pulse reads elements 2 1, ... ,, 5,6,7 elements and 5, connected in series through the core of the preparation of element 1 1 and a diode, the element is prepared. Element 5 is prepared with the first clock pulse. With a clock pulse, the elements .. ,,, 5,6,8 are read again. As a result, circulation 1 starts in the first digital cell of the counter. In the same way, with the arrival of the following pulses of addition 1, the counter transitions to state 2, 3, etc. After the tenth impulse of addition 1, the transfer element 7 is prepared, from the output of which, through the preparation winding of the zero digital cell element, the input signal enters the high-order counter. This signal is received by the high-level counter as an attachment 1, and in the counter in question begins Circulation 1 in a zero digital cell. A subtraction pulse 1 coinciding in time with a fifth clock pulse, as well as an increment pulse 1, element 5 is read and element 6 is prepared. Six with the clock pulse, the elements are read, .. ,, 5,6,7. If before the subtraction pulse 1 was applied, the counter was, for example, in state 9 (i.e., by the time the sixth clock pulse appeared, an element was prepared), then elements and 6, connected in series through the element preparation winding and the decoupling diode, , The first clock prepares the element 5. The third clock pulse reads the elements. ,, 1 0,5,6,8. The elements and 5, connected in series through the element preparation winding and the diode 16, prepare the element. The fourth clock prepares the element 5. The sixth clock pulse re-reads the elements, ... ,, 5,6,7, as a result of which the element is prepared, i.e. Circulation 1 begins. In the eighth digital callback. In the same way, with the advent of the following, the subtracts the subtraction of the meter to 7, 6, and so on. After the tenth pulse of subtraction 1, the transfer element 8 is prepared, from the input of which a signal is sent to the low-order counter through the preparation winding of the element of the ninth digital cell. This signal is received by the low-order counter as a signal for subtracting 1, and in the counter in question, the head of the ninth digit is a circulating cell. To reset the setting pulse counter to O, received via bus 16 and coinciding in time with the second clock pulse, 1 is written to the element and element 5 is read, into which 1 was previously recorded by the first clock pulse, 1 1, elements are read by the third clock pulse. ,., and the series-connected element 5. But since element 5 has already been transferred to the state O by the impulse to be set to O, the entries 1 to one of the elements,. , no matter what state the counter was on the eve of the impulse 7 set to O. The sixth clock pulse reads the elements, o.2 9,, 5 and the element will be written 1 into the element. The first clock pulse writes 1 to the element 5. the elements are read again by a clock pulse and 5, in which case 1 is written to the element, t, e, circulation 1 begins in the zero digital cell of the counter. Claims of the invention Reverse counter on ferrite transistor elements, containing. two registers, key elements of circulation and advancement 1, and transfer element 1 to the high-order counter, in which the output of each element of the first register is connected successively through a decoupling diode and the recording winding of the element of the corresponding digital cell of the second register with key element of circulation 1 to digital through the decoupling diode and the recording winding of the next digital cell element with the key element of the 1% advance; of the second register and reading of the key element of circulation 1 in a serial connection, the input counting pulse bus is connected to the windings of reading the key element of circulation 1 and writing the key element of the advance 1, the output of the element of the first register of the last (senior) digital cell is connected in series through winding transfer element 1 to the older digit counter with key element 3 advance 1, and the transfer element output through the write winding of the element of the zero digital cell of the first register connect The transfer signal bus 1 is connected to the high-order counter, characterized in that, in order to expand the functionality, the output of each element of the second register is connected in series through the coupling diode and the recording winding of the element of the corresponding digital cell of the first register to the key element of the circuit also through the diode and the write winding of the previous digital cell of the first register with key element of advancement 1, the output of the zero digital cell element of the second register is connected in series through the winding of the recording of the transfer element 1 to the low-order counter with the key element of advancement 1, and the output of this element through the winding of the recording of the element of the last (highest) digital cell of the second register is connected to the transfer signal bus 1. into the low-order counter, the first and fourth clock buses the signals are connected to the write winding of the key element of the circulation 1, the third clock signal bus is connected in series with the read windings of the key elements of the circulation 1, advance 1 and the first register, the sixth bus clock signal is coupled in series with the windings of the read key element circulation 1, 1 and the advance of the second register. Sources of information taken into account in the examination 1 "USSR Author's Certificate No. 251275, cl. H 03 K 23/32, Ob.Ob.68. 2. USSR author's certificate No. 517166, cl. H 03 K 27/00, 2b „12Л. / f ft w  I J3 3 - I