SU907808A1 - Device for adding and subtracting pulses - Google Patents

Description

The invention relates to electrical measuring technology and can be used in the construction of qi ((devices that include a device for the lyricization of nonlinear characteristics of frequency sensors or transducers). A device for changing the frequency of pulses containing a multivibrator, a trigger, a single vibrator, and an MLI element 11 is known. low temperature stability due to the presence of analog functional nodes and low accuracy due to the fact that the output pulses are multivibr the pulses of the input signal are not synchronized and their simultaneous appearance at the input of the bi-stable circuit leads to the loss of one pulse at the output of the device.Also, a device for adding and subtracting pulses is known, which contains two input buses, two control buses, two triggers of the device, two I elements, the OR element and the trigger, the direct and inverse outputs of which are connected respectively to the first inputs of the first and second elements AND, the second inputs of which are connected to the first input bus and to the trigger zeroing input, the installation input the unit of which is connected to the second input bus, the third inputs of the first and second And elements are connected respectively to the first and second control buses, the outputs of the first and second And elements are connected respectively to the first input of the OR element and to the counting input of the first trigger of the device, whose direct output connected to the second input element OR, the output of which is connected to the counting input of the second trigger of the device 2. The disadvantages of the known device are low functional

opportunities, since it does not ensure its operability with arbitrary duty cycles and arbitrary mutual phase shift of input and corrective impulses received through input buses due to the uncertainty of the trigger state when signals are sent to its installation inputs, and low accuracy due to the absence of impulse blocking on addition by the signal that sets the measuring interval of the device, which leads to the switching of the instrument triggers (counter) by correction pulses beyond the limits of the measurement unit interval (counter).

The purpose of the invention is to expand the functionality of the device and increase its accuracy,

The goal is achieved by the fact that the device for adding and subtracting pulses contains two input buses, two control buses, two instrument triggers, two AND elements, an OR element and the first trigger, the direct and inverse outputs of which are connected respectively to the first inputs of the first and second elements. And, the second inputs of which are connected to the first input bus, the third inputs of the first and second elements And are connected respectively to the first and second control buses, the outputs of the first and second elements And are connected respectively to the first the input of the OR element and with the counting input of the first trigger of the device, the direct output of which is connected to the second input of the OR element, the output of which is connected to the counting input of the second trigger of the device, the second trigger and the third element I are entered, the first input and output of which are connected respectively with the direct the output of the first trigger and the reset input of the second trigger, the direct output of which is connected to the second input of the third element And and to the information input of the first trigger; the second control bus is connected to the fourth input of the first element And that, the clock inputs of the first and second flip-flops are respectively connected to first and second input buses.

FIG. 1 is a schematic diagram of the device; in fig. 2 - timing charts of the device.

The device contains a trigger 1; elements 2 and 3; the element OR k, trigger 5 and 6 of the device (the first bits of the counter); element 7, trigger 8, input buses 9 and 10, control buses 11 and 12.

The input bus 9 is connected to the clock input of the trigger 1 and the first inputs of the elements 2 and 3, the second inputs of which are connected respectively to the inverse and direct outputs of the trigger 1, the information input of which is connected to the direct output of the trigger 8 and the second the input and output of which are connected respectively to the direct output of the trigger 1 and the reset input of the trigger 8, the clock input of which is connected to the input bus 10, the third inputs of the elements 2 and 3 are connected to the control bus 11, the control bus 12 is connected to the fourth input And 3, outputs., And 2 and 3 elements are connected respectively to the counting input of the device trigger 5 and to the first input of the OR element, the second input and output of which are connected respectively to the forward output of the device 5 trigger and to the counting input of the trigger 6 of the device .

Timing diagrams of signals, respectively, on the input tires 9 and 10 are marked 13 and Ik; timing diagrams of the signals at the direct outputs, respectively, of the flip-flops 8 and 1 are labeled 15 and 16; timing diagrams of signals, respectively, at the outputs of the elements And 7, 2, 3 are marked 17-19 (Fig. 2).

The device works as follows.

The input clock of trigger 1 receives input frequency pulses from bus 9. The clock input of trigger 8 receives impulses of correction frequency from bus 10 in the initial state (Fig. 2, time) and the trigger 1 and trigger 8 are in the logical O state. ,, so . switching of trigger 1 is prohibited by a logical O signal at its information input, and switching of trigger 8 is allowed, since a logical signal O is present at its reset input. At the time point .t, the trailing edge of the correction frequency pulse arrives and a trigger 8 is triggered with a delay equal to switch

FIG. 2, diagram 15). Trigger 8 triggers a resolving potential at the information input of trigger 1, which is triggered from the trailing edge of the input frequency pulse at time t, 2 with a delay equal to its switching time (Fig. 2, diagram 16). Trigger 1 triggers AND 7, which, by the reset input, returns trigger 8 to the zero state (Fig. 2, charts 15 and 17) and the positive potential at information input of trigger 1 disappears. Therefore, when the next input frequency pulse arrives (Fig. 2, the time tj) trigger 1 returns to the zero state and remains there until the next permitting potential arrives at its information input. If there is a single potential on the control bus 12 (control subtract-add), then the output pulse of trigger 1 through the element 3 and the element OR k is fed to the counting input of the trigger 6 of the device (Fig. 2, diagram 19). This is equivalent to applying two pulses of the input frequency to the input of the trigger 5 of the device; an operation is performed to add a single pulse to the pulses of the input frequency. If there is a zero potential on the control bus 12, pulses at the output of the And 3 element are absent, and the output pulse of the trigger 1 blocks one pulse of the input frequency by the And 2 element (figure 2, diagram 18). In this way, the operation of subtracting a single pulse from the pulses of the input frequency is performed. If a control bus appears on the control bus 11 (the reference bus of the measuring interval), then the elements 2 and 3 are closed, i.e. the transmission of pulses to triggers 5 and 6 was blocked. I

The device according to the present scheme maintains operability at any

duty cycle of the input signal pulses and frequency correction pulses. At the same time, the moments of arrival of the correction frequency pulses can be arbitrary and unsynchronized with the input frequency pulses. As a result, the functionality of the proposed device is greatly enhanced in comparison with the known one.

In the proposed device, due to the connection of the bus with one of the inputs of the element I, there is no passage of the correction frequency pulses to the input of the second trigger outside the measuring interval, which ensures a higher accuracy of the proposed device compared to the known one.

Claims (2)

1.Patent UK tr 1332292, Cl, AND 03 K 5/00, 1973. 2. Authors certificate of the USSR № «503 6, cl. H 03 K 13/20, 1975 (prototype). /four th