SU794713A1 - Frequency-phase comparator - Google Patents

Description

the first input is greater than the second; pulse frequency at the first input is less than at the second; the pulse frequency at the first and second inputs are equal.

Consider the operation of the comparator in the first mode. In the initial state at the direct outputs of 1K-triggers 4, 5, 6 - the logical “O.

The pulses arriving at the first input of the comparator will switch 1K, the trigger 4 to the logical state 1, the pulses arriving at the second input of the comparator will return the lK trigger 4 to the zero state. Since the pulse frequency at the first input is greater than at the second, there will be a periodical situation when in the time interval between two pulses at the first input, there will be no pulses at the second input. The first of these two pulses will cause the setting to “1 1K-flip-flop 4, while from its direct output the logical “1” signal will go to the second 1-input of the trigger 5 and allow it to switch to “1.

When the second pulse arrives at the first input, the 1K flip-flop t will be set to "1. From its inverse output, a logical signal “Oh, forbid, ayush,” is set to “About trigger 4.” Secondary appearance at the first input of two pulses, between which there will be no pulse at the second input, will result in setting to “1 1K- trigger 6, while from the inverse output of the 1K-trigger 6 to the third K-inputs of the 1K-flip-flops 4, 5 will receive a logical signal “Oh, prohibiting them setting in“ O.

Thus, in the mode when the pulse frequency at the first input of the comparator is greater than at the second, 1K flip-flops 4 and 5 are constantly in the logical "1" state, and the 1K flip-flop 6 switches to "1 pulses from the first input the comparator and in “O - pulses from the second input.

At the direct output of the 1K flip-flop 5 (comparator output) there will be a constant logical 1 signal.

In the second mode of operation of the comparator, when the pulse frequency at the first input of the comparator is less than the second, a situation will periodically arise when in the time interval between two pulses at the second input of the comparator, no pulse will arrive at the first input. As a result, regardless of the initial state of the comparator, a moment will come when the triggers 4-6 will be in the logical state "O. At the same time, from the direct output of the 1K-trigger 4, the second 1-inputs of the 1K-triggers 5 and 6 will receive a logical signal “Oh, forbid, setting them to“ 1. When a pulse arrives at the second input of the comparator, the 1K-flip-flop 4 will be set to the state "O", and when the pulse arrives at the first input of the comparator, the W-flip-flop 4 will return to the state "1. Triggers 5 and 6 will be permanently in the state "O and on the direct output of the U-trigger 5 (at the output of the comparator) the logical signal" O.

In the third mode of operation of the comparator,

at the same pulse frequency at the first and second outputs of the comparator, the 1K-flip-flop 4 is set to the state "1, 1K-flip-flop 6 to the state" O, and the U-flip-flop 5 will switch to the state "1

impulses arriving at the first input, and in the state “About impulses received by them at the second input.

Thus, at the output of the comparator, square-wave pulses with a filling factor proportional to the phase difference of the signals at the first and second inputs of the comparator will be generated.

In particular, when the delay time 3 of the signal at the second input is changed relative to the first input from "O to G (G is the pulse following period at the first input), the fill factor / C3 of the signal from the direct output of trigger 5 will change from 0 to 1.

When t О, 3 О, i.e., at the direct output of the 1К-flip-flop 5 the logical signal "O" constantly holds. At tz T, kz 1, i.e., at the direct output of the 1K-flip-flop 5, the signal logical 1 1 is constantly present.

In the frequency equality mode, trigger 4 will be constantly in the state "1, and trigger 6 in the state" O. If trigger 4 is in the state "O, those with coincidence in time of pulses on the first and

the second inputs of the comparator, triggers 4-6 will take the state "O," 1, "O, respectively. The arrival of the next pulse to the first input of the comparator will cause the switching of the flip-flops 4, 5 and 6 of the state "1," 1 and

"Oh, if the first pulse arrives at the second input of the comparator, then the triggers 4, 5, 6 switch to the state" O, "O," O, respectively. Similarly, if the initial states of the triggers 4, 5, 6 were "1," 1, "O, then the simultaneous arrival of pulses at the inputs of the comparator will switch the triggers 4, 5, 6 to the state" 1, "O," 1, respectively. Then, if the first pulse arrives in time at the first input of the comparator, then the triggers 4, 5, 6 change their state to "1," 1, "1, and if the first pulse is at the second input of the comparator, then the triggers 4, 5 , 6 will accept the state "1," Oh,

"ABOUT.

It can be seen that with simultaneous arrival of pulses at the inputs of the comparator, a short-term deviation from the normal operation of the comparator occurs, which is eliminated with the arrival at any of

next pulse that does not coincide in time with the pulse at the other input of the comparator.

Claims (1)

1. USSR author's certificate in application number 9145657, cl. H OZK 9/04, 1975.