SU907693A2 - Device for disconnection of electric network at asynchronism occurence between twoparts of power system - Google Patents

Description

to current sensors. The device returns to its original state after the circuit is disconnected or the asynchronous stroke is terminated. Moreover, the disadvantage is that the condition for starting an asynchronous stroke detection automatic detection in the time interval when the first derivative of the current envelope has a negative polarity so that to ensure the necessary accuracy of switching off the circuit to the minimum of the current of the biennium by starting the delay unit at the end of the negative half-wave. The known automatic devices for detecting asynchronous operation do not have such organs controlling the sign of the first derivative of the beating current. The purpose of the Invention is to increase the speed and accuracy of the device. This goal is achieved by the fact that the device is additionally equipped with a NOT logic and an AND logic, the output of which is connected to the input of the first pulse expander, the first input — to the output of the first OR logic and the input of the logic circuit — NOT, and the second input is intended to input the enable signal from devices for automating the detection of asynchronous operation, and the output of the logic circuit is NOT connected to the start-up start-up unit. At the same time, the advance timing start block contains the first and second zero-bodies responding respectively to the positive and negative polarity of the signals whose inputs are combined and connected to the output of the first differentiating unit, the logic circuit IL delay block, pulse extender, input which is connected to the output of the second null-organ, and the first logic circuit AND, the output of which is connected to the first input of the logic circuit OR, and the second input to the output of the pulse expander, the second logic circuit AND, the output of the The second is connected to the input of the delay unit and to the second input of the OR logic circuit, the output of which is connected to the first input of the second logic circuit AND, the second input of which is connected to the output of the above logic circuit NOT, and the output of the first zero-body is connected to the first input of the first logic circuit I. In FIG. 1 shows a diagram of the device; in fig. 2 - voltage plots at the outputs of the main blocks of the circuit - for two cases: when (Fig. 2, a) and at ton Tu / (Fig. 2.6) Here tjjp is the specified advance time; Tt is the period of the current bending envelope. The device contains a block 1 for determining the current envelope of the beating, a first differentiating block 2 for extracting the first derivative of the envelope of the current for the beating, block 3 for launching an advance time to obtain at the output of the device a signal with a predetermined advance time with respect to the moment of disconnection, the first 4 and second 5 blocks measurements and instant memory values of the current envelope of the beats, which continuously measure the instantaneous value of the envelope, measured by the starting time, and intended to be measured before starting from block 3; respectively for operation of the device at and at tjjp,, / the first comparator 6, which is triggered when the signal from block 4 exceeds the signal from block 1, the second comparator 7, which is triggered when the signal from block 5 drops below the signal from block 2, the second 8 and the third 9 differentiating blocks that form narrow pulses at the beginning and end of the signals from the outputs of comparators b and 7, respectively, the first 10 and second 11 blocks of a half-wave rectifier, extracting pulses formed respectively at the back edges of the signals from to comparators b, and 7, the first logical OR gate 12, the NAND gate 13, AND gate 14, the first expander. 15 pulses and the actuator 16. The start-up start-up unit 3 contains the first 17 and second 18 null-organs designed to form square impulses. Of the positive and negative half-waves of the first derivative of the beating current envelope, the pulse expander 19, the first logic circuit AND 20, respectively. , a logic circuit OR 21, a second logic circuit AND 22 VI delay block 23 for setting a preset time setting. The device works as follows. In the normal mode, when there is no asynchronous operation and there is a periodic current at the input of the unit 1, a constant voltage is formed at its output, which corresponds to a zero slip frequency. At the output of block 2, there is no signal, since the first derivative of a constant value is zero. Therefore, the output of the block 3 start the signal also will not. In this case, blocks 4 and 5 work in the mode of large-scale amplifiers with transmission coefficients KI-LYK 1st., Where 0.05-0.1. This is necessary so that the comparators b and 7 do not work when there is no start from block 3, but

also for the correct functioning of the device in modes with op 5 / 2. / and c. Since the comparators 6 and 7 do not work, all subsequent blocks and the executive body are not excited either.

16 does not work. The operation of the measuring body 16 will not occur even in the case of the passage of interference from block 1 through blocks 4 or 5 to the circuit 14, since the second input of the logic circuit 14 does not have a signal from the automatic detection of asynchronous motion.

When an asynchronous stroke occurs in the network, the current at the input of block 1 contains a beat envelope varying with the slip frequency W. In block 1, the beat envelope is selected and fed to block 2, where it differentiates and feeds into zero-organs

17 and 18.

If the negative half-wave comes first, then the first impulse is a null organ 18, this pulse is expanded in the expander 19 for a time sufficient to close the possible pause between the termination of the signal from the null organ 18 and the appearance of the null organ 17 so that Short-term coincidence of the signals at the inputs of the AND 20 logic circuit is provided. The signal from the output of the AND 20 circuit through the logic circuit OR 21 and the logic circuit 22 is fed to the delay block 23 and simultaneously stored by feedback from the output of the circuit 22 to the second input of the circuit. LEE 21. Said passage 23 to block the signal is possible only in the presence of a logic one signal at the second input of AND gate 22 from the NAND gate 13, which always takes place in the absence of signal at the output of block 23, i.e., when block 4 and 5 do not have a signal at the start inputs. At the output of block 23, the signal appears after a time equal to the required advance time tg. If the positive half-wave arrives from block 2 first, then the first zero-body pulse 17 begins to form a rectangular impulse 17. However, the signal from the zero-organ 17 goes through circuit 20 , since the second input of the circuit AND 20 signals a Vits from the expander 19 only after the termination of the signal from the null organ 17. Such a circuit ensures the passage of a positive signal only after the end of the previous negative signal, thus preventing the unit 23 from starting in arbitrary moment of the positive half-wave of the first derivative of the beat current envelope.

If the slip frequency is such that at the moment of launching from block 23 of blocks 4 and 5, the memory organs are turned on and the input circuits are disconnected. As soon as the signal from current 1 becomes higher than the signal from the output of the block, comparator 6 will operate and remain in this state until the signal from block 1 becomes lower than the signal from block 4.

From the moment block 4 starts up and the signal ends at the output of the comparator 6, the comparator 7 remains in an unheated state, since the voltage at the output of block 5 does not exceed the voltage from block 1. The signal from the output of the comparator 6 (for a duration equal to T5 is 2 ton) is differentiated in block 8, at the output of which narrow pulses of positive polarity are produced at the time of the signal from the comparator 6 and negative at the time of its termination. With a half-wave rectifier 10, only a negative pulse is selected, corresponding to the point in time at which a signal should appear to control the switch, taking into account the required lead time. The signal from the output of the rectifier 10 through the logic circuit OR 12 enters the first input of the logic circuit AND 14 and passes further to the input of the pulse extender 15, if at the second input of the circuit AND 14 there was a logical unit, indicating

0 that the automatic detection of the asynchronous course of work. At the same time, a pulse from the output of the OR circuit 12 is fed to the input of the NOT 13 logic circuit, thus providing a briefly 5 temporary zero signal at the second input of the AND circuit 22, which returns the delay block 23 to the initial state and clears the memory in blocks 4 and 5. The output signal scheme

0 and 14, extended in the expander 15, is fed to the executive body 16. If the second input of the AND 14 circuit at the time of arrival of the pulse of the OR circuit 12 was zero, then the signal to the executive body 16 will not pass,

5 and after resetting of blocks 3, 4 and 5, a new cycle starts from the beginning of the next beat period (Fig. 2, a). The moment of reset of the block 3 coincides with the moment of termination of the signal at the output of comparator 6, and due to the memory being turned off in blocks 4 and 5, they switch to the scale amplifiers mode. At the same time, there will be no changes in the state of comparator 7, since

5, the signal from the output of block 5 remains below the signal from block 1.

If the slip frequency is such that 7, then start-up from blocks 4 and 5 will occur in the reduction area

0 bending current envelope (Fig. 2.6). This means that the signal at the output of block 4 after memorization at the time of launch will remain above the signal from block 1 and the comparator 6 will remain

Claims (2)

5 unworked. Comparator 7 will work almost immediately after the start of block 5, as soon as the signal from block 5 becomes higher than block 1 The signal from comparator 7 passes through differentiating block 9 and out: 11 to the second input logical cxeNBJ OR 12 and further as described for op. The device works correctly the same in cases where ton g. The use of the proposed device allows increasing the accuracy of switching off an asynchronous stroke to a minimum of the beating current, which will facilitate the operation of high-voltage switches and reduce network overvoltages and reduce the time from the moment of detection of the asynchronous run to its disconnection. The technical and economic effect from the application of the proposed device is achieved by increasing the stability of power systems and individual objects, as well as increasing the service life of electric power equipment. Claim 1. Device for disconnecting an electrical circuit in case of synchronism violation: between two parts of the power system according to aut. St. 811403 is different in that, in order to improve speed and accuracy, it is additionally equipped with a logical NOT circuit and a logical AND circuit, the output of which is connected to the input of the first impulse expander, the first input - to the output of the first logical circuit OR , the second input is intended for input of the enabling signal from the automatic device for detecting asynchronous operation, and the output of the logic circuit is NOT connected to the start time trigger unit. 2. The device according to claim 1, characterized in that the start-up start-up block contains the first and second zero-bodies responding respectively to the positive and negative polarities of the signals whose inputs are combined and connected to the output of the first differentiating unit, a logic circuit OR, delay unit, pulse expander, the input of which is connected to the output of the second zero-organ, and the first logic circuit AND, the output of which is connected to the first input of the logic circuit OR, and the second input - to the output of the pulse extender, the second logic circuit AND, the output of which is connected to the input of the delay unit and to the second input of the logic circuit OR, the output of which is connected to the first input of the second logic circuit AND, the second input of which is connected to the output of the mentioned logic circuit NOT, and the output of the first zero-body connected to the first input of the first logical scheme I. Sources of information taken into account during the examination 1. USSR author's certificate on the model 2736837/07, cl. H 02 J 3/24 ,. 1979