SU887037A1 - Sorting and monitoring automatic machine - Google Patents

Description

An array assembled on the flip-flops 7 is connected to the binary-code-to-voltage converter 8, the output of the latter being connected to the actuator 4 directly or through an amplifier.

Constructive execution of key schemes can be different, in particular, such as shown in the drawing, i.e. the first key scheme 9 can be performed on the AND gates, the first inputs of these elements are connected to the outputs of the binary adder 5, and the second inputs are connected to the outputs of the counter-drive 10 with a capacity, the input of which through the logical element 11 is connected to the gate, with the output of the measuring-coding converter 1. The second key diagram can be performed on the elements 12, in which the first inputs are connected to the output Converter 6 is connected, the second are connected to each other, and then directly to the output of the storage drive 10 and through the inverter 13 to the I element, and through the one-shot 14 to the first inputs of the triggers 7, the second inputs of which are connected to the outputs of the elements 12. Bus reset counter drive 10 is connected to a time relay 15.

A static code to binary code converter 6 is constructed as follows. One of the possible expectations of the monitored parameter is set for a certain number of tests L, which is encoded by a uniform binary code, thus obtaining a certain set of A units and zeros, which is one of the possible combinations of the statistical code. The maximum permissible probability value of a false address is set and, based on the expected expected parameter of the monitored parameter, the minimum permissible cycle time is calculated, the voltage value is calculated which, when applied to the actuator 4, provides the calculated cycle time, encodes the value of this voltage with a binary code and obtains some set B .

Other possible mathematical expectations of the controlled parameter are set, other sets A and B are obtained similarly, after all this a table of correspondence is made and a code converter is built according to it using known methods, in which each set A corresponds to a certain set B.

The machine works as follows.

The controlled product is conveyed by the transport mechanism to the measuring-coding transducer 1, and then to the sorting mechanism 3. After measuring each product, the code combination appearing at the outputs of the transducer 1 enters the storage device 2, and then the sorting device

mechanism 3. When the product after measurement reaches this mechanism, it is ready for use (in the appropriate state) and the product is sent to the appropriate sorting compartment. This is repeated every cycle. In addition, a pulse appears at the gate output of the measuring-coding converter 1 during each cycle, which overflows the counter 10 through the open logic element 11 to the input of the summation of the binary adder 5 to the counter-tip 10. From the outputs of the binary adder 5 information

in the parallel code, it enters the inputs of the converter 6 if the corresponding elements of the first key circuit 9 are open, but does not go further, since the second key circuit does not let it through.

The drive-accumulator 10 operates in the subtractive mode, starting from the zero state to the state corresponding to the number N of tests. If the number V of tests is set to a multiple of 2, then after N tests

A binary set A will be removed from the outputs of the first key circuit 9, which corresponds to the mathematical expectation of the parameter being monitored. In triggers 7 some memory is remembered.

previous information This happens for N cycles. Upon reaching N cycles, the drive-accumulator 10 overflows, at its output the signal "1 (before it was" O), tia the output of the inverter 13

O and the 11 element ceases to pass the gating pulses into the iu drive counter and to the input of the summation resolution of the binary adder 5. At the time being, the outputs of the first key circuit Y have a set A, one of those that correspond to a certain expected value of the monitored parameter. At the same time, the accumulator counter overflow signal 10

causes the elements 12 to pass from the converter 6 to the triggers 7 the code set B resulting from the conversion of the set A. The pulse coming from the storage drive 10 through the one-shot 14 erases the previous information in the triggers 7.

After that, the code set B, applied to the triggers 7, comes from them to the converter 8 of the binary code to voltage,

and the latter enters the electric drive 4. The rotation speed of the electric drive varies, and the speed of the camshaft also varies. The performance of the machine varies according to the change.

mathematical expectation of the controlled parameter. At certain time intervals, the relay 15 returns the accumulator 10 to the initial zero state and the performance tuning is repeated in accordance with the new mathematical expectation of the monitored parameter. The likelihood of false addressing at the same time remains equal to the maximum allowable.

The use of a scheme that determines the mathematical expectation of a controlled parameter reduces hardware costs without decreasing the productivity and quality of sorting of the control and sorting machine.

Claims (1)

1. USSR author's certificate No. 593756, cl. On 07C 5/08, 1976.