SU883895A1 - Device for detecting extermal numbers - Google Patents

Description

(54) DEVICE TO SEARCH FOR EXTREME NUMBERS

The invention relates to automation and computing technology and can be used to control the parameters of technical objects in computers and information-measuring devices when solving problems of prompt and reliable information processing. A device for searching extreme values of parameters is known, comprising a polling switch co-switch, a register bit consisting of a binary counter and a decoder, a controlled oscillator, a trigger trigger, bit elements AND and OR, registers for writing values of monitored parameters, bit logic blocks, the two input elements 11 whose inputs are connected to the outputs of the switch and logic bit blocks, the recording blocks of the extreme value of the parameter, and its address, which allows determining the parameter having kstremalnoe value and its address. The closest to the proposed technical solution is a device for searching extreme values, containing a block of registers, a group of elements OR, a first group of elements NOT, a first group of elements AND, a second group of elements AND, a start block, a block for fixing a parameter value, a block for fixing an address, the common elements are AND and OR, and the outputs of the first bits of all the registers are directly, and the outputs of the remaining bits of the registers are connected to the inputs of the corresponding elements of the OR group, the outputs otorgh connected to the inputs of group of elements and the data inputs of NOT of the AND of the first group, the control input coupled to uprgll yuschim input member and the second; the group and with the first output of the startup block, input 3 of which is connected to the input of the device, the outputs of the elements And the first group are connected to the information inputs of the latch parameter block, the control input of which is connected to the second output of the trigger block and the control input of the address fixing block, information the inputs of which are connected to the outputs of the elements AND of the second group, the first code of the group of Elements is NOT directly, and the rest of them - through the second bit of the elements AND are connected to the first inputs of the bit elements OR of all the isters, the second inputs of which, except for the corresponding to the first bit of all the registers, are connected to the outputs of the corresponding first bit elements AND, the second inputs of the bit elements SH, corresponding to the first bit, (connected to its output directly, the outputs of the bit elements OR of each register , except for the last one, are connected to the inputs of the first and second bits and the next bits, the bits of the elements of the last bit of all registers are connected to the information ones (the inputs of the second group of elements I G2. The disadvantages of the known devices are the limited functionality of the possibilities, which is not possible to find the minimum value of the parameter, as well as maximum and linear differences. The purpose of the invention is to expand the functionality of the device by determining the extreme values of numbers and extreme differences. The goal is achieved by those in the device for searching-extreme numbers, which contains triggers result register, address register, parameter registers, extremal value registers, groups of elements AND, OR, NOT, elements AND, OR, subtraction unit, These analyzers, with the direct and inverse outputs of each i th digit of the j th register of parameters, where I 1,2, ... J <1,2 ,, .., K, n is the number of bits, K - the number of numbers connected to the first and second inputs, respectively, of the JJ-th bitwise analyzer j, then the discharge, the device start input The unit is connected to the input of the unit one above the first trigger, the direct output of which is connected to the first input of the first element I, the output of which is connected to the input of the installation xB, the unit state of the second trigger, the direct output of which is connected to the first input of the second element And, the output of which connected to the input of the unit in a single state of the third trigger, the first output of the j-th bit of the analyzer of the K-th bit of the g-a is connected to the third input of the j-th bit of the analyzer (K + 1) -th bit, where K 1,2, ..., (p-1), the output of each j.-ro bit by bit The first analyzer of the nth digit is connected to the jth input of the address register, each jth output of which is connected to the first input of the thth AND element of the first group, the output of each of which is connected to the j-, my input of the result register jth output the second outputs of the jth bits of the jth bits are connected to the inputs of the i-th elements of the OR group, the output of each of which is connected to the first input of the i -th element of the second group and through the i-th element NOT - with the fifth inputs of bit-analyzers i- of the second bits, the output of each i-ro element AND the second group is connected to the input of the i-ro bit of the first extremum register, each first output of which is connected to the first input of the i-ro element AND of the third group, the output of each of which is connected to the input the i-th bit of the second extremum register, each i-th output of which is connected to the first input of the th element of the fourth group, the output of each of which is connected to the input of the i-th bit of the third extremum register, the outputs of the extremum registers are connected to the block inputs subtraction ENA connected to the inputs of the first OR gate whose output is connected to the WTO. the inputs of the first and second elements And to the first input of the third element Nick the first input of the fourth element And, the output of the third element And connected to the inputs of the installation In the zero state of the trigger, the direct outputs connected to: the inputs of the second element OR, the output of which is connected to the second the inputs of the elements of the first group and with the first inputs of the same size as the anchtisers, the direct output of the first trigger is connected to the first inputs of the fifth, sixth, seventh, eighth and ninth elements I, and the inverse output to the first input of the tenth element And, the output of which is connected to the control inputs of the result register and the extremum register, the direct output of the second trigger is connected to the second inputs of the eighth and ninth, And elements, the outputs of which are connected to the second inputs of the third and fourth elements of the elements, respectively, the inverse output of the second trigger is connected to the second inputs of the fifth and sixth elements And, the output of the fifth element And is connected to the second inputs of the elements And the second group, the direct output of the third trigger is connected to the third input of the ninth element is And, and its inverse output is the third inputs of the fifth and eighth elements And to the second input of the seventh element And whose output is connected to the seventh inputs of the analyzers, the output of the sixth element And is connected to the eighth inputs of the parser analyzers. In addition, each bitwise analyzer contains AND, OR elements, wherein the first and second inputs of the bit analyzers are connected to the first inputs of the first and second AND elements, the outputs of which are connected to the inputs of the first OR element, whose output is connected to the first input of the third AND element, the output of which is connected to the first input of the second OR element and to the second output of the bit analyzer, the output of the second OR element is connected to the first output of the bit analyzer, the third input of the bit analyzer is connected to The third input of its element I is connected to the first input of the fourth element I, the output of which is connected to the second input of the second head of the head assembly, the fourth input of the bit analyzer is connected to the second inputs of the first and second elements I, the fifth and sixth inputs of the bitwise analyzer are connected with the second and third inputs, respectively, of the fourth element, And, the seventh and eighth inputs of the bit analyzer are connected to the third inputs of the first and second elements, I. Fig. I shows the block diagram of the device; 2 is the same as a bit analyzer. The device contains triggers 1-3, register 4 results, register 5 addresses, registers 6, 6,2, ..., 6f parameters, registers 7-9 extreme values, groups of elements And 10 1C, 112, 13 .. 13n iJ, iJ2.5-- -5ts 5 cops H 14-2 I, a group of elements OR 22,22 ,, .., 22 „, elements OR 23 and 24, elements NOT 25 ,, 25, .. ,, 25 ,, elements AND 26 and 27, subtraction unit 28, bitwise analyzers, in.oni 7Q 2-9,. . . , 29; 29,2, j, .. |, (L5 29, .. ,, 29 |, each of which contains an element ШШ 30, elements И 31 and 32, elements ИГИ 33, elements И 34 and 35. The device works as follows: In the initial state, the triggers 1-3 of the registers are in zero states. Elements AND 14-16 are closed with zero potentials from the direct outputs of the triggers-3. Elements And 20 and 21 are closed with zero potentials from the direct outputs of the triggers 1 and 2. On the second information inputs of bit analyzers, there are potentials of a logical zero, since the AND 32 elements are closed by a zero with the control L guide output of the second OR gate 24 and AND gates 31 are closed with the zero potential output of the AND) W 30. Before coming into registers pulse Run 6 records recorded parameter values of parameter values. With at the pulse start Trigger goes into one state and at the output of the element And 20 there is a single potential, which, attached to the first control inputs of the discharge analyzers 29, causes the opening of the discharge elements of the WB 30 and at the outputs of these elements The values of the parameters recorded in registers 6 appear. Also, the unit potential from the direct output of flip-flop 1 opens the element OR 24 and the element AND 14. The unit potentials from the outputs of elements SHSh 24 and 14 prepare the bit elements AND 32 bit analyzers 29 and n The first group of elements And 10, respectively, to trigger. At the outputs of the bit elements OR 33 first bit anaggizers

29, logical potentials appear depending on the values of the parameters recorded in registers 6 of recording the values of the parameters.

The first element OR, 22 of the first group allows you to determine the extreme value of the parameter in the first bit, which is inverted by the LEVE 1m element NOT 25 of the first group and applied to the inputs of the bit elements AND 32 bit analyzers 29 of the first bit. The signals from the output of the bit elements OR 33 of the first bit are fed to the inputs of the bit elements AND 31 and 32 of the bit analyzers 29 of the second bit. The second element of the 22 SHS of the first group allows determining the extreme value of the parameter in the second category.

Since zero potentials are present at the outputs of the bit elements And 31 of the bit analyzers 29, since the second trigger of the registers 6 of the parameter values are in zero states, then the output of the second element F1E 25 of the first slot has the potential of a logical unit. This potential opens the elements AND 32 bit analyzers 29 and at the output of the elements OR 33 bit analyzers 29 there are logical potentials,. These signals interrogate bit elements And 31 bit analyzers 29 of the third bit. At the outputs of the discharge elements OR 33 of the third discharge potentials are set.

. RGI 1. Reg. 1. 1. Proc., Pf ,, 4. 0P .5 O, Pr.fe O, P.- 1, PP, in 0.

Thus, the third, fourth, fifth, sixth, and eighth registers 6 of recording parameter values are excluded from the subsequent analysis. The Pp, P, and Pf signals interrogate the bit elements AND 31 of the bit analyzers 29 of the fourth bit. At the output of the discharge elements OR 33 bits of the analyzers 29 fourth discharge potentials are established

 one,

Oh, R Oh,

WG4 0

Gp

g

 0, Py. 0

Ppj. oh, g and, gu, and, guad r,

Thus, all registers are excluded, except the first one, in which the extreme (maximum value) is recorded. The signal from the output of the discharge element SHTI 33 of the fourth discharge of the analyzer 29 of the first register 6 and the parameter values 29 passed through the other discharge analyzers 29 causes the first trigger to switch in the register of fixing the address. The appearance of a single potential at the output of the register 5 of the address fixation causes the opening of the first element And 13 of the fourth group, the unit potential from the output of which translates the trigger of register 4 of the fixed result of the atom in comparison to the one state and from its inverse of the output removes the potential of a logical zero, which closes the elements OR of 30 bit analyzers 29 of the first register 6 of writing parameter values.

Simultaneously with the recording in the register 4 of fixation of the results of a single potential, the first OR control element 23 of the register 6 write registers of parameter values is opened, and the potential of the logical unit from its output through the value register AND parameter 17 controls the register of value 6 registers, translates trigger 2. control polling registers 6 write parameter values to one state. Simultaneously with switching trigger 2 of polling control of registers 6 to write parameter values, a single potential from the output of the element OR 23 polling control of registers 6 of recording parameter values, through address fix register 27 of address fix 5, causes the address fix register 5 to switch to the zero state.

Claims (2)

Thus, after the first polling cycle, the register in which the extreme value of the parameter is written does not participate in the subsequent cycles. This extreme value of the parameter is written to the extreme recording register 7 (maximum parameter value. By switching, the trigger 2 controlling the polling of the registers to write parameter values is one the potential closes the AND control element 20 for polling the registers of writing parameter values and the AND 14 control for writing to the write register of the maximum value. Simultaneously The same potential opens the polling register control element AND 21 of the parameter value writing registers and the write control register 15 into the small value register parameter register. 15 The unit potential from the output of the parameter polling register write register 21 control is fed to the second control inputs of the analyzers 29 and at the outputs of the bit elements I.11 and 30 there appear inverse values of the parameters recorded in registers 6 of recording the values of the parameters. The operation of the device when connecting inverse bits of the triggers of registers 6 to write parameter values is similar to that described. The found extreme (the minimum value is fed to subtractor 28, where the maximum difference is determined. After switching trigger 3 of the poll control registers to write parameter values, the device determines another extreme (first after minimum) value that is fed to subtractor 28, where and the minimum difference is determined. After the occurrence of a single potential at the output of the element OR 2 of the control of the polling of the registers of the recording of parameter values, the element And 18 opens, the control of the polling of the registers recording parameter values and a single potential from its output goes to the setup inputs to the zero state 1-3 of the polling register control write the parameter values and converts them to the zero state. Thus, the proposed device allows processing the weight of an information array in three cycles and set the extreme values of the parameters, as well as the maximum and minimum differences, which significantly expands the functionality of the device and can be used in automatic process control systems process for the purpose of preprocessing information. Claim 1. Device for searching extreme numbers, containing triggers result register, address register, parameter registers, extreme value registers, AND, OR, NOT element groups, AND, OR elements .10 subtraction unit, serial analyzers, and the inverse outputs of each i-ro bit of the j-ro parameter register, where, 2, ..., n, j 1,2K, n is the number of bits, K is the number of numbers, are connected to the first Bbw and BTopbiM inputs, respectively, j-ro j-ro bit analyzer, device launch input is connected to unit installation input th state of the first flip-flop, a direct output of which is connected to the input of the first element pervm AND, whose output is connected to the input of a single installation state of the second flip-flop, a direct output. which is connected to the first input of the second element I, the output of which is connected to the installation input to the unit state of the third trigger, characterized in that, in order to expand the functionality of the device by determining the extreme values of numbers and their extremal differences, therein the first output j- ro of the bit analyzer of the K-th bit is connected to the third input of the j-ro bit of the analyzer of the (K + 1) th bit, where, 2, ..., (n-1), the output of each j-ro of the bit analyzer of the n-th digit of the connection to the j-th input of the address register, each j-th output of which is connected to the first input of the | -th element AND of the first group, the output of each of which is connected to the j-th input of the result register, the j-th output of which is connected to the fourth inputs of the j-th parser analyzers, the second outputs bit analyzers of the j-th bits are connected to the inputs of the i-th elements of the OR group, the output of each of which is connected to the first input of the i-element of the AND group of the second group and through the t-th element NOT to the fifth inputs of the analyzers of i- output bits, the output of each i-ro element And the second group is connected to the input of the th digit of the first register of extrema, each i-th output of which is connected to the first input of the i-ro element AND of the third group, the output of each of which is connected to the input of the bit of the second register of extrema, each i-th output of which is connected to the first the ir.p input of element AND of the fourth group, the output of each of which is connected to input1 1 house of the i-th bit of the third extremum register, the outputs of the extremum registers are connected to the inputs of the subtraction unit, the outputs of the address register are connected to the inputs of the first OR element, whose output is connected to the second} 4 inputs of the first and second elements I and to the first input of the third element I and to the first input of the fourth element I, the output of the third element I connected to the installation inputs. To the zero state of the triggers, the direct outputs are connected to the inputs of the second element 1, the output of which is connected to the second inputs of the elements of the first group and to the first inputs of the bit analyzers, the direct output of the first trigger is connected to the first inputs of the fifth, sixth, seventh, eighth and ninth elements of I, and the inverse output to the first To the first input of the tenth element I, the output of which is connected to the control inputs of the result register and extremum registers, the direct output of the second flip-flop is connected to the second inputs of the eighth and the second I elements, the outputs of which are connected to the second inputs of the third and fourth elements of the zlemeito; accordingly, the inverse output of the second trigger is connected to the second inputs of the fifth and sixth element I, the output of the fifth element I is connected to the second inputs of the elements And the second group, direct: the output of the third trigger is connected to the third the third input of the ninth Element I, and its inverse output to the third inputs of the fifth and eighth elements AND to the second input of the seventh element I, the output of which is connected to the seven inputs of the P1x1 analyzer, the output of the sixth element And is connected to the eighth input analyzers. 2. The device according to claim 1, 1 and 2, so that in it, each bitwise analyzer contains the elements H, OR, and the first and second inputs of the bit analyzers are connected to the first inputs of the first and second elements AND The outputs of which are connected to the inputs of the first OR element, the output of which is connected to the first input of the third AND element, the output of which is connected to the first input of the second OR element, and to the second output of the parser analyzer, the output of the second element. OR is connected to the first output of a bit analyzer, the third input of the bit analyzer is connected to the second input of the third element AND to the first input of the fourth element AND, the output of which is connected to the second input of the second element OR, the fourth input of the bit analyzer is connected to the second inputs of the first and second Elements I, the fifth and sixth inputs of a bitwise analyzer are connected to the second and third inputs of the fourth element, respectively. And the seventh and eighth inputs of the bitwise analyzer are connected to the third inputs. I will give the first and second elements I. Sources of information taken into account during the examination 1. USSR author's certificate No. 534762, cl. G 06 F 7/02, 1975. 2. USSR author's certificate, No. 525083, cl. G 06 F 7/04, 1975 (prototype).