SU871162A1 - Digital coordinate converter - Google Patents

Description

The invention relates to a computational technique and is intended to be calculated from the known, codes of the polar coordinates and the measured value of the codes of its rectangular coordinates X and y and vice versa. A device 11 is known, the operation of which is associated with the processing of information by a number of pulses. The closest in technical essence and the achieved result to the invention is a device for converting rectangular coordinates into polar 12, containing registers, switches, a digital converter, a multiplier, an adder and a control unit. The disadvantage of these devices is low speed. The purpose of the invention is to increase speed. This goal is achieved by the fact that a second functional converter and an arithmetic unit are inserted into a digital coordinate converter containing two registers, two switches and the first functional converter. The groups of the bit outputs of the first and second registers are connected respectively to the first and second groups of inputs of the first switch. The output group of the first switch is connected to the input group of the arithmetic unit. The first and second registers are connected respectively to the first and second inputs of the first functional converter, the third input of which is connected to the first output of the arithmetic unit and to the first output of the device. The group of bit outputs of the second register and the group of outputs of the first functional converter are connected respectively to the first and second groups of inputs of the second switch. The group of outputs of the second switch is connected to the group of inputs of the second functional generator "and the first group of outputs of the device. The group of outputs of the second functional converter is connected to the third group of inputs of the first switch. The group of outputs of the arithmetic unit is connected to the second group of outputs of the device and to the group of inputs of the first functional converter. The second output of the arithmetic unit is the second output of the device. The input of the second switch is the first control input of the device. The second control input of the device is connected to the first and second inputs of the first switch and the arithmetic unit. The third and fourth control inputs of the device are connected respectively to the third input of the arithmetic unit and the input of the second functional converter. The fourth, fifth, and sixth inputs of the arithmetic unit are, respectively, the first, second, and third clock inputs of the device. Structure diagram of the device at. shown in the drawing. The device contains registers 1, 2, switches 3, 4, functional converters 5, b, arithmetic unit 7. In the drawing, control inputs 8-11 of the device are indicated, clock inputs 12-14 of the device, output 15 of register 1, output 16 of register 2, device output 17, output group 18 of register 1, output group 19 of register 2, output group 20 of functional converter 6, group of outputs 21 of functional converter 5, output group of 22 commutator 3, output group of 23 devices, group of output 24 of device, output 25 of the device. When performing the computational operation, multiplication and division are performed with the arithmetic unit 7, the calculation by the argument (angle C) is the function of the sine or coordinate, the functional transducer 6, and the calculation by the argument (tg M of the function, (i.e. Angle, F) functional converter 5. Each of the calculations is performed in a cycle according to the contents of registers 1, 2 according to the signals generated at the outputs 17, 24 and 25 of the arithmetic unit 7 (the output signal 17 produces an information signal C17 and the output signal 25, A2.5 such that if the arithmetic. B Lock 7 is occupied by the calculation, then, and if it is free, then) and by the input control and synchronizing signals: the control code of the two-digit code .a and 2 (al and a2 | the digit digits of the code) coming from inputs 8 to the control inputs of the switch 3 and the arithmetic unit to the control signals P9 / P10 and nil, respectively, coming from inputs 9, 10 and 11 to the control inputs of the switch 4, the functional converter b and to the control input of the arithmetic unit 7; input pulse IV12, start pulse I313 and clock pulses, TI14, respectively, coming from inputs 12, 13 and 14 to the corresponding inputs of the arithmetic unit 7. In each cycle of performing a direct conversion or inverse transformation, two time slots can be distinguished, in each of which steady state from output 15 and from outputs 18 of register 1 is removed information signal C15 and F18 function code F18, from output 16 and outputs 19 of register 2 - information signal C16 and function code F19, from outputs 20 of functional converter 6 - function code and F20, from outputs 21 functional transducer 5 - F21 function code from the outputs 22 and 23 of the commutators 3 and 4 - F22 function code and function code F23, output 17, output 24 and output 25 of the arithmetic unit 7 - C17 information signal ,. function code F24 and output control signal P25. There are some analogies when performing a direct transformation and an inverse transformation in the coordinate converter. In this connection, the description of the work in the performance of direct and inverse transformations will be carried out as far as possible, in parentheses, information relating to the description of the work in the inverse transformation). The coordinate transducer of jcodes H and V (codes X and V) during each cycle of the forward (inverse) transformation performs the computation in the first cycle of the code X (code V), and in the second - the code V (code Y). Before beginning: In the next cycle of the forward (inverse) transformation, the arithmetic unit 7 is occupied (generates a signal), in registers 1 and 2 there are codes and Ф19 М (codes and signals С15 and .. are generated, input 8 receives code 00, and input 9 and 10 signal and (signals and). With the help of signals П9 the functional converter b generates a code (code Ф2 0 when i). Using the code to & mmutator 3 outputs a count (code) to the arithmetic unit 7. The direct (inverse) conversion cycle starts at the time of generation by the arithmetic unit 7 of the signal, according to which the outputs 17 and 24 of the arithmetic unit 7 yield the result The signal F24 is removed from the arithmetic unit 7, the signal (signal) and the first impulse IV12 are received. By the signal () the arithmetic unit is activated to perform the multiplication (division) operation, and by the first IV 12 the code is entered into the memory of the arithmetic unit 7 F22 (code F22 X). After the termination of the first IV12, a code 10 (code) is applied to the inputs 8, a Cos f code (code V) is set to the inputs of the arithmetic unit 7, and a second IW and the first IZ13 trigger pulse is passed to the arithmetic unit 7. For the second IV12, the F22 SoC code (F22 code) is entered into the memory of the arithmetic unit A. After the end of the first IV13, input 10 receives a signal., Input 8 receives the code 00 (OS17 code) Converter 6 is occupied by calculating the code from the signal and code (Code F20 from the signals,, C15, and codes F24, and the arithmetic unit 7 starts to perform a multiplication operation by codes and Cos (division operations by X and V codes). Upon termination of each OF13, the arithmetic unit 7 performs (when) the multiplication operation for the duration of the time -tv, (for.) the division operation for the time duration of t cases clock pulses TI14. When performing a direct conversion through time Conversion 6 generates the H code, and through time and the eithmetic unit 7 generates a signal and the F24 code. The signal is removed from the arithmetic unit 7 and the second conversion cycle begins, which is similar to the first one, except for the fact that in the second cycle in memory of the arithmetic unit 7, the V- and sin codes are entered. Therefore, at the end of the direct conversion cycle, the arithmetic unit 7 generates a signal and F24 Sin code. This signal is used to remove the arithmetic block 7 of the F24 V code and start the coordinate converter for the subsequent cycle, either direct or inverse. If the length of time for entering information into the arithmetic unit 7 is neglected, then the duration of the direct conversion performance Tz can be estimated by the expression In the first cycle, when performing the inverse transformation through time -fc, the grandfather arithmetic unit 7 generates a signal, code Ф24 (С- (4) and signal where, k 1, if IXKIv / Tak Kak, S1b (, and the input control code is OK, then some time after the first division operation is performed, the code F22 RC + K-U, the converter is set on the inputs of the arithmetic unit 7 5 generates a code, switch 4 - ko The converter 6 is the + KSin4 code. After setting the codes to the arithmetic unit 7, the third IV12 comes, after which it ends. To the inputs B, code 10 is supplied, the code Ф22 Ф20 КСозЧ j-KSinf is supplied to the inputs of the arithmetic unit 7 and the second IV13. On the third and fourth IV12, the code F22 КХ + к- is entered into the arithmetic unit 7 and the code Ф22 КСойЦ- KSinV and on the second pulse IZ13 the first clock ends and the second clock of the inverse converter begins; those. F23 code is removed and the arithmetic unit 7 is started to perform a division by code (JCX + KV) and code (KC (f + + KsiM4). Therefore, at the end of the inverse transformation cycle, the arithmetic unit 7 generates a signal and code N / M, F24 K co5T lyuT With this signal, the signal is removed from the arithmetic unit 7 of the code and the coordinate converter is started for the subsequent cycle, either inverse or direct conversion The application of the invention improves the speed of the device. th two registers, two switches and a first functional converter, characterized in that, in order to increase its speed, it contains a second functional converter and an arithmetic unit, with r-dumps of the first and second registers of the discharge outputs connected to the first and second groups of inputs the first switch, the output group of the first switch is connected to the input group of the arithmetic unit, the outputs of the first and second registers are connected respectively to the first and second inputs of the first function A third converter, the third input of which is connected to the first output of the arithmetic unit and the first output of the device, the group of bit outputs of the second register and the group of outputs of the first functional converter are connected respectively to the first and second groups of inputs of the second switch; the group of outputs of the second switch is connected to the group of inputs of the second functional transformer and with the first group

the device outputs, the output group of the second function converter is connected to the third group of inputs of the first switch, the device output group and the input group of the first function converter, the second output of the arithmetic unit is the second device output, the second switch input is the first control input of the device, the second control The device input is connected to the first and second inputs of the first switch and the arithmetic unit, the third and fourth control inputs of the device

Connected respectively to the third input of the arithmetic unit and the input of the second functional converter, the fourth, fifth and sixth inputs of the arithmetic unit are the first, second and third clock inputs of the device, respectively.

Sources of information taken into account in the examination

1. Author's certificate of the USSR 656069, cl. G 06 F 15/32, 1976.

2. US Patent 3,952,187,

cl. G 06 G 7/22, published, 1977 (ProtothioZ.

Claims (1)

Claim A digital coordinate converter containing two registers, two commutators, and a first functional converter, this is because, in order to increase its speed, it contains a second functional converter and an arithmetic unit, and the outputs of the first and second registers are connected respectively with the first and second groups of inputs of the first switch, a group of outputs. . the first switch is connected to the group of inputs of the arithmetic block, the outputs of the first and second registers are connected respectively to the first and second inputs of the first functional converter, the third input of which is connected to the first output of the arithmetic block and the first output of the device, the group of bit outputs of the second register and the group of outputs of the first functional converter are connected respectively to the first and second groups of inputs of the second switch, the group of outputs of the second switch is connected to the group of ode of the second functional converter and with the first group of device outputs, the group of outputs of the second functional converter is connected to the third group of inputs of the first switch, the group of device outputs and with the group of inputs of the first functional converter, the second output of the arithmetic block is the second output of the device, the input of the second switch is the first control the input of the device, the second control input of the device is connected to the first and second inputs of the first switch and arithmetic eye, third and fourth control inputs of the device are respectively connected to the third input of the arithmetic unit and the input of the second function converter, fourth, fifth and sixth inputs of the arithmetic unit 5 are respectively first, second and third clock inputs.