SU866737A1 - Switching device - Google Patents

Description

(54) COMMUNICATING DEVICE

I

This invention relates to automation and computing.

Known switching device containing memory blocks, registers and control and switch P The closest to the technical essence of the proposed is a switching device containing memory blocks, information and the first and second control to the inputs of each of which are connected respectively with the same information input buses, the query input bus and the output of the control unit, and the information and the first and second control outputs are connected respectively to the same name group of information inputs c, to the same first control input of the main switch and the output bus of confirmation, as well as a block of registers, the control input of which is connected to one of the outputs of the control unit, and the first output is connected to the second

the control input of the main switch, each of the information output groups of which are connected to the information output buses of the same name, and each of the control 5 outputs connected to the launch output bus of the same name, while the first input control unit buses of C2.

10 The lack of known devices is low speed.

The aim of the invention is to improve the speed of the switching device.

, 5 This goal is achieved due to the fact that blocks of signs, comparisons and direction choices are entered into the switching device, an address register and an additional switch, whose information inputs are connected to acknowledgment input buses, the control input is connected to the first output of the register block, and the outputs are connected to the third control inputs of the memory unit 38 and the second group of inputs of the control unit, the third group of inputs of which are connected to the outputs of the attribute block, whose information inputs are connected to the information inputs m buses and control input - to an output control unit which outputs are also connected with the control inputs of the address register and the comparator and the select direction, the outputs th us

which are connected to the information inputs of the register unit, the second outputs of which are connected to the first information inputs of the direction selector, the second information inputs of which are connected to the output of the comparison unit, the first and second groups of information inputs of which are connected respectively to the information outputs .

FIG. 1 is a block diagram of a switching device; in fig. 2 Functional block of features; in fig. 3 - the same direction block; in fig. 4 - the same control unit.

The device contains memory blocks I, information and the first and second control inputs of each of which are connected respectively to the information input buses of the same name 2, the input request bus 3 and the output of the control unit 4, and the information and the first and second control outputs are connected respectively to the same the group of information inputs of the same first control input of the switch 5 and the output bus 6 confirmation, block 7 registers, the control input of which is connected to one of the outputs of block 4 of control, and The left output is connected to the second control input of the switch 5, each of the information output groups of which is connected to the information output buses of the same name 8, and each of the control outputs connected to the same launch output bus 9 of the first control unit 4 of the control unit is connected to the input buses 3 of the request , switch 10, whose information inputs are connected to confirmation input buses 11, the control input to the first output of register unit 7, and the outputs are connected to the third control inputs of memory 1 and the second group of input of control unit 4, the third group of inputs of the registers, the second inputs of which are connected to the first information inputs of the direction selector 15, the second information inputs of which are connected to the output of comparison unit 14, the first and second groups of information inputs of which are connected respectively to the information outputs of the blocks I memory and 18 address register outputs.

The feature block 12 (Fig. 2) contains a register of 16 features, comparison elements 17, outputs 8) connected to the third group of inputs of control unit 4 (not shown).

The direction selection unit 15 (FIG. 3) contains information buses 19-24 connected to the outputs of the comparison unit 14 (not shown), information buses 25-29 connected to the outputs of the register block 7 (not shown), elements 30 and inverters 31 , and also tires 32-36,

Block 4 controls (Fig. 4) contains the elements And 37-39, inverters 5 40, triggers 41 and 42.

The operation of the switching device is as follows.

Claims (2)

One of the input busses 3 of the request receives a request signal. This signal is fed to the corresponding memory block 1 and to the input of the control block 4. From the output of memory block 1, a confirmation signal is received on the output bus 6 of confirmation 5. Thereafter, the information input bus 2 records in the memory 1 the address of the required switching device. This address arrives at comparison unit 14 and is compared there with the own address of the switching device, which arrives with the address register 13. Information about the comparison result is fed to the direction selection unit 5-15. Depending on the result of the comparison and on the state of the switch 5, the direction selection block I5 generates the address of the 7th or 7th terminal connected to the outputs of the 12 signs, the information inputs of which are connected to the information input buses 2, and the control input to one of the outputs of the control 4 , outputs. Which are also connected to the control inputs of the address register 13, the comparison unit 14 and the direction selection unit 15, the outputs of which connect to the information inputs of the other output block 7. If the addresses match, an output is selected that is connected to the information receiver. In the case when the address of the required switching device is greater than the own address of the switching device, you choose an output connected to the switching device with a larger private address, and in the case where the address of the required switching device is less than the own address of this switching device, the output that connects to the switching device is selected device with a smaller private address. The address of the selected output goes to register unit 7 from which it is transmitted to switches 5 and 10. Thus, memory unit 1 is connected to the corresponding output and input of the switching device. The aaifpoca signal from the output of memory block I goes to switch 5 and then to the selected output, indicated by block 7 of registers. After receiving the confirmation of the confirmation signal on the input bus I1, the address of the required switching device enters the information output bus 8. At the same time, a confirmation signal is sent to you one bus 6 of the confirmation, which allows you to write to memory 1 in the next information layer. After that, the switching device enters the relay mode and the incoming information is sent further along the already laid path. In this mode, the information sent to the previous switching device causes the appearance of a request signal from the neighboring switching device on the input bus 3. This switching device responds with the appearance of a confirmation signal on the output bus 6, after which information from memory block 5 of the previous switching device is written into memory block} of this switching device. In this case, in addition to the block 1 of the memory, the information goes to the block 12 of signs, which, if it determines the end of the message, for example by a special code combination, generates a signal that arrives at block 4 of the control, which ultimately leads to destruction connection established in switches 5 and 10 after passing the last word of information. At the time of termination 76. recordings in memory block 1 generates a request signal, which arrives at the next launch device 9 on the subsequent switching device and suppresses the confirmation signal, which arrives at the output confirmation bus 6. When a confirmation signal is received from a neighboring (subsequent) switching device via the input confirmation bar 11, the information from memory block 1 is read, and after the reading is completed, the confirmation signal is received via the output bus 6 confirmation. Thus, the transmission of information through the switching device is carried out in packets. At the beginning of the packet there is a header containing the address of the desired switching device. At the end of the packet is an indication of the end of the message. Switching is asynchronous. Block 12 features works as follows. Informational input buses 2, accompanied by a request signal, are received on the input buses 3 of the request, information is fed to one of the inputs of the comparison elements 17. At the other input of the comparison elements 17, a message end code is received from the register of 16 features. On comparison elements 17, the received information is compared with the end-of-message code. If the incoming information word matches the end message code, the comparison element 17 generates a signal that appears at one of the outputs 18. The appearance of the signal at the output 18 means that the last word of the packet containing the terminator sign received on this information input bus 2 messages. Each comparison element 17 serves its information input bus 2, since the information on the individual inputs of the switching device is independent and appears asynchronously. The operation of the direction selection unit 15 is as follows. The address in the packet header consists of two components X and Y. In block A of the comparison, the distance between these two components is compared. The result of the address comparison may be the following signals:. leaving X own address of the switching device is greater than leaving X addresses from the packet header, X - component X of the switching device's own address less than component X of the address of the packet, X - component X of the switching device's own address equal to the component X of the address from the header package. Similarly for the component Y, Y, U, U. These signals in the direction selection block 5 are received via the corresponding buses: X - via bus 19, X - via bus 20, bus 21, U, - via bus 22, X - via bus 23 , U - by bus 24; Moreover, in block 15 of choice nap | The signals are received by the input buses from the register block 7, which contain information about the state of the switching device outputs: bus 25 - about the state of the output Increment by X, bus 26 about the state of the output Reduction by X bus 21 - about the state of the output Reduction U, bus 28, exit state; Decrease along U; and bus 29, exit state. Coincidence. Suppose that the signal is on the wils on bus 19 and on bus 22. If the output is Increased in X free, then on bus 25 the signal is equal to a logical one and on the output bus 32 of the direction selector 15 there is a logical one, which means that the output Commutation Device Increment in X, while the signal on bus 22 is ignored. But, if the output Increment in X is occupied (on the bus 28 is a logical zero) and the output is free in Decrease in Y, then the signal of a logical unit appears on the output bus 36, which means: output is selected Decrease in Y. In case of both required outputs of the switching device the choice of direction will be made at the moment of release of one of the required outputs. The control unit 4 operates as follows. At the initial time, the triggers 41 and 42 are in the zero state. Suppose that the signal of the logical unit arrived at the third input bus 3 request. This signal, after being processed by the elements AND 37, will set the third trigger 41 to the one state. The signal of the logical unit from the unit output of the third trigger 41 through the third element AND 39, since the third trigger 42 is 3 in the zero state, goes to the corresponding output bus. At the moment when the request signal is zeroed, the output of the third inverter 40 turns on the signal of a logical unit that, having passed through the third element E 38, sets the third trigger 42 to one state, and this will cause the signal on the corresponding output bus to zero. and it will remain so no matter what changes in the signal occur on the input bus 3 of the query. In the future, this state will be maintained until the third triggers 41 and 42 are set to zero states by a signal from the block of 12 features. Thus, the control unit 4 from the request signal sequence selects the first request signal accompanying the packet header and uses it as a signal that the comparison unit 14 starts and the direction selection unit 15 starts. Information about the selected output of the switching device is stored in block 7 of the registers. In block 7 of registers, each block 1 of memory has its own register. Switching is carried out using switches 5 and 10 under the control of register unit 7. Switch 10 commutes input confirmation buses 11 coming from neighboring switching devices to corresponding memory blocks 1, and switch 5 switching start output buses 9 and informational to code buses 8 of corresponding memory blocks 1 with input buses of neighboring switching devices. The connection of this memory block 1 with the corresponding input (output) of the switching device is saved only for the time it passes through the information packet. When the last word of the packet passes, the block of 12 signs is triggered, by the signal of which in block 7 of registers in the register corresponding to the given memory block, the exit code is erased and this output is released. Thus, the introduction into the switching device of the blocks of signs, comparison and choice of direction, address register and additional commutationly increased tator allowed speed. The invention The switching device containing the memory blocks, information and the first and second control inputs of each of which are connected respectively with the same information input bus, the sanRoC input bus and the output of the control unit, and the information and first and second control outputs are connected respectively to of the same name rjjynne informational and of the same name, the first control inputs of the main switch and the confirmation output bus, as well as a block of registers, the control input of which is with one of the outputs of the control unit, and the first output is connected to the second control input of the main switch, each of the information output groups of which is connected to the information output buses of the same name, and each of the control outputs connected to the launch output bar of the same name, while the first a group of inputs of the control unit is connected to the input request buses, characterized in that, in order to increase the speed, the feature, comparison and direction selection blocks, the address register and an additional com A device whose information inputs are connected to confirmation input buses, the control input is connected to the first output 1 of the pegistres block, and the outputs are connected to the third control inputs of the memory blocks and the second group of inputs of the control unit, the third group of inputs are connected to the outputs of the characteristic block , information codes of which are connected to information input buses, and the control input - to one of the outputs of the control unit, the outputs of which are also connected to the control inputs of the address register and comparison and selection blocks directions, the outputs of which are connected to the information inputs of the register unit, the second outputs of which are connected to the first information inputs of the direction selection block, the second information inputs of which are connected to the output of the comparison unit; the first and second groups of information and Hbtx inputs are connected respectively to the information outputs of the memory blocks and outputs address register. г Sources of information taken into account in the examinations. 1. Kalev A.V. Homogeneous switching register structures, M., Soviet Radio, 1978, p. 212 2.-USSR Copyright Certificate No. 503235, cl. G 06 F 7/00, 1975 (prototype). FI.1 nineteen. 20. 21 12. 25. V 25 2627 28 29 Phage .2 eg -53 -ZA -35 -36 before Phie. "3