SU864580A1 - Devic for testing binary counter - Google Patents

Description

(54) BINARY COUNTER CONTROL DEVICE

one

The invention relates to control-measuring and computer technology and can be used for controlling binary counters during mass production.

Counter control devices are known that contain matching schemes, a delay element, fl flip-flops.

The disadvantage of such devices is a large monitoring time, the value of which is determined by the counter size. ,

The closest in technical essence to the invention is a meter control device containing triggers, AND, OR elements, delay elements and elementary counters .2 1.

A disadvantage of this device is the large amount of time spent on control.

The purpose of the invention is to reduce the time control.

This goal is achieved by the fact that a device for controlling a binary computer, containing a delay element, an input connected to the counting input of a controlled counter, and an AND element, is entered a decoder, a valve block and a register, with the outputs of the block

the valves are connected to the corresponding installation inputs of the controlled counter, the control inputs of the valve block are connected to the corresponding outputs of the register bits, the second inputs of the valve block are connected to the output of the delay element whose input is connected to the Control terminal of the device and the control

To the input of the register, another input of which is connected to the input terminal of the device, the output of each digit of the controlled counter is connected to the input of each digit of the decoder, the output of each digit of the decoder is connected to the corresponding input of element I.

The drawing shows the functional diagram of the device.

20

The device contains a delay element 1, an element 2, a controlled counter 3, a decoder 4, a valve block 5, a register 6.

The device works as follows.

25 way.

In the initial state, in all bits of the counter 3, the memory elements of the decoder 4, register 6 is set to O (the setting circuit in O to

Fig. 30 is not shown in the drawing). After arriving at the counting input of counter 3 and the control input of register 6 of the first impulse of control, the equilibrium code 000. ,, 001 with one unit at the lowest time de appears at the outputs of counter 3. From the outputs of counter 3, the generated code enters the inputs of the decoder 4. If the input code of the decoder 4 receives a monitored code with one unit, the corresponding output bus appears on the corresponding output bus (in this case, the bus associated with the lower bit of the decoder 4) element am ti.

Simultaneously with the formation of the code in the counter 3, the arrival of the first impulse control takes place. The installation code in the register 6 is generated. . I

The first control pulse also arrives at the input of delay element 1, the output of which it arrives before the arrival of the second control pulse.;. The delayed control pulse opens the gate unit 5 through the second inputs, and the code 000 ... 001 recorded in register 6 is rewritten into counter 3, confirming its state.

Under the action of the second control pulse, at the output of counter 3, an equilibrium code with one unit reappears, but the indicated unit is already shifted one bit in the direction of the higher digit of the counter. The generated code (000 ... 010 is also an equilibrium and is decrypted by the decoder 4, as a result of which a second signal appears at the second output recorded by the memory element corresponding to this output. Therefore, after the first two control pulses arrive, The units are in a single state.

In the shift register 6, according to the described algorithm, the second current control code sets the following current code 000 ... 011, which is installed in the control unit 3 by the second control pulse, delayed by the first control element 1, through the valve block 5.

The current set code 000 ... 011 written to counter 3 is not decrypted by decoder 4, since it is in the area of forbidden combinations.

With the arrival of the third control pulse arriving at the counting input of the counter 3, the unit is transferred to the third bit and at its outputs an equilibrium code is formed from 1 to the third bit de 00 ... 0100.

At the corresponding output of the decoder 4, a signal is detected by the memory element.

Under the influence of the next; jth control pulse, the described control process 5 repeats, i.e. at the output of the decoder 4 control results, the equilibrium code is fixed, fixed by the corresponding memory element, and in the pause between

The o {j + 1) -M control pulse in counter 3 sets a code, | In which the number of units located is equal to the sequence number of the control pulse j-ro.

In the absence of defects in the monitored counter, by the end of the monitoring all the memory elements must be in a single state, as a result of which the output of the AND element appears a pulse indicating the correct operation of the counter and the windows. his control.

It follows from the above that for monitoring an n-bit counter using the proposed device

5 control requires only (n + 1) counting pulses to be fed to its input, which significantly reduces the time needed to control the counter.

Claims (2)

1. USSR author's certificate No. 392502, cl. J F 11/00, 1971. 2. USSR author's certificate number 451198, to. H 03 K 21/34, 1975 (prototype).