SU864516A1 - Pulse shaper - Google Patents

Description

I

The invention relates to a pulse technique and can be used in devices for multiplying the pulse frequency.

A pulse shaper is known that contains a static trigger, the outputs of which are connected to the first inputs of two coincidence circuits, the source of input pulses, the output of which is connected directly to the second input of the first coincidence circuit, and to the second input of the second coincidence circuit via an inver OR, the inputs of which are connected to the outputs of the first and second matching circuits, and the output through the delay device is connected to the counting input of the static trigger 1.

A disadvantage of this device is the impossibility of the formation of both pulses during the time of action of the input pulse.

The closest in technical essence to the invention is a pulse shaper, containing the element I and the first integrating RC circuit, the input of which is connected to one of the inputs: the element AND and the bus of the input pulses, and the output with the counting trigger input, the inverse output of which is connected through the second integrating circuit to the single input, the direct output of which is the output of the device. The device emits two pulses at its output during the duration of the input pulse. In this case, the duration of the first pulse is determined by the first integrating chain, the interval between pulses is determined by the second integrating chain. Thus, the duration of the second pulse depends on the duration of the input pulse (2.

A disadvantage of this device is the impossibility of forming both pulses of the same duration during the time of action of the input pulse.

15

The purpose of the invention is to equalize the durations of the formed pulses.

The goal is achieved by the fact that in a pulse shaper, containing two delay elements, a trigger and an AND element, one of

The first inputs of which are connected to the direct output of the trigger, and the second - to the other, entered the first pulse separation unit, three AND-NOT elements and an additional AND element, and one of the inputs of the first AND-NOT element and an additional AND element are interconnected , with the input bus and the setup inputs of the trigger and the selection unit of the first pulse, the counting input of which is connected to the output of the element I, and the output connected to one input TiWTbero of the element I-Sh; and through the second delay element - to the second input of the additional element AND, the output of the additional SOUTH element AND, through the first delay element is connected to the second input of the first AND-NOT element whose output is connected to the counting trigger input and to one input of the second AND-NOT element, the second the input of which is connected to the inverse output of the trigger, and the output to the second input of the third NAND element, the output of which is connected to the output bus of the device. The drawing shows the functional diagram of the pulse former. Pulse generator, contains the element And I, the delay element 2, the element And-NB 3, trigger ger 4, the element And 5, block 6 of the selection of the first pulse, the delay element 7, the elements AND-NO 8 and 9. One of the inputs of the elements And 1 and 5 are interconnected, with the input of the device, with one of the inputs of the element AND-NE 3 and the installation inputs of the trigger 4 and the block 6 of the discharge of the first pulse, the second input of the element And 1 through the delay element 7 is connected to the output of block 6 and to the input from the inputs (element AND-NOT 9. The output of the element AND 1 is connected through the element of delay 2 to the second input of the element 3 the output of which is connected to the counting input of the trigger 4 and one input of the element IS-HE 8; the inverse output of the trigger 4 is connected to the second input of the element AND IS NOT 8, and the direct output to the second input of the element 5 whose output is connected to the counting input unit 6. The output of the element IS-NE 8 is connected to the second input of the element IE-HE 9, the output of which is the output of the device. The pulse driver operates as follows. A single input pulse allows operation of the counting input of trigger 4 and block 6, at the output of the block 6, the pulse and the input pulse is repeated. m. At the output of the element I I, the input pulse also repeats over time T. After this, from the output of the element I I, a zero inhibitory potential arrives. Thus, at the output of the element And 1, a termed input pulse is formed; and the element of delay 2 through time T forms it at its output. The coincidence of the leading edge behind; a pulse with a single potential of the input pulse at the inputs of the element AND-NOT 3 switches the trigger 4 through the counting input. The zero differential from the direct output of trigger 4 through the element 5 switches the block 6, which is restored to its initial state by a zero potential on the setup input at the end of the input pulse. At the output of block 6, an inverted pulse of duration T was formed, which, in turn, is inverted by the open element AND-HE 9 and the first pulse of duration T is formed at the output of the device. Over time T, the delay element 7 again forms at its output the potential arriving at the input of the element AND 1, at the output of which a single impulse is formed again, arriving through the delay element 2 at the input of the element IS-HE 3, which inverts it. The trigger 4 is switched again on the counting input, and at the output of the AND-HE element 8, a zero pulse of duration T is formed, which is inverted into a queue by the open element H-HE 9 and arrives at the output of the device. Thus, at the output of the device, two pulses are formed with a duration T and the interval between them is also T. The device stops working before the next pulse arrives, and the zero potential of the interval between the input pulses returns block 6 to its initial state, and the device prepares for the formation of the next pair pulses with the arrival of the next input pulse. Thus, the C) pulse shaper generates two pulses of the same duration for the duration of the input pulse. The device can also be used as a pulse number doubler. The formula for the new Pulse Driver, which contains two delay elements, a trigger and an element, one of the inputs of which is connected to the trigger output and the second with an input bus, because, in order to equalize the duration of the formed pulse, the selection block of the first is entered into it. impulse, three NAND elements and an AND additional element, and one of the inputs of the first NAND element and an additional AND element are interconnected with the input thickness and the installation inputs of the trigger and the first impulse extraction unit a, the counting input of which is connected with the output of the AND element, and the output is connected to one input of the third I-NB element and through the second delay element to the second input of the additional element AND, the output of the additional element AND through the first delay element is connected to

the second input of the first NAND element, the output of which is connected to the counting trigger input and the ODI input of the second NAND element, the second input of which is connected to the inverse output of the trigger, and the output to the second input of the third NAND element, the output of which is connected to output the device.

Information sources,

taken into account in the examination

1. USSR author's certificate number 455468, cl. And 03 K 5/04, 1973.

2. USSR author's certificate number 621076, cl. H 03 K 5/01, 1977,

R

Claims (1)

Claims 40 A pulse shaper containing two delay elements, a trigger and an And element, one of the inputs of which is connected to the direct output of the trigger, and the second to the input bus, ₄₅ ρ is distinguished by the fact that, in order to equalize the duration of the generated pulses, a block for selecting the first pulse, three AND-NOT elements and an additional AND element are entered into it, and one of the inputs of the first AND-NOT element and the additional AND element are interconnected, the input bus and the setup inputs of the trigger and the block selection of the first pulse, the counting input of which is connected to the output of the element AND, and the output is connected to one input of the third element AND-NOT and through the second delay element to the second input of the additional element And, the output of the additional element And through the first delay element is connected to 864516 the second input of the first NAND element, the output of which is connected to the counting trigger input and one input of the second NAND element, the second input of which is connected to the inverse output of the trigger, and the output to the second input _{5 of the} third NAND element, the output of which is connected to the output bus device.