SU860043A1

SU860043A1 - Information retrival device

Info

Publication number: SU860043A1
Application number: SU792778153A
Authority: SU
Inventors: Олег Павлович Босый
Original assignee: Предприятие П/Я А-3759
Priority date: 1979-06-08
Filing date: 1979-06-08
Publication date: 1981-08-30

Description

Изобретение относится к автомати· ке и вычислительной технике и предназначено для выбора информации.The invention relates to automation and computer technology and is intended to select information.

Известно устройство для выбора информации, содержащее входной регистр, блок сравнения, накопитель и адресный блок fl].A device for selecting information containing an input register, a comparison unit, a drive and an address unit fl] is known.

Наиболее близким к предлагаемому является устройство для выбора информации, содержащее последовательно соединенные первый регистр, первый блок памяти и второй блок памяти, блок синхронизации, соединенный с первьм регистром и первьм блоком памяти, блок сравнения, первый йход которого соединен с первый выходом второго блока памяти, первый выход с первым входом шифратора, второй выход - со вторым входом шифратора, блок счетчиков, первый и второй входы которого соединены соответственно с первым и вторым выходами второго блока памяти, выход - с первыл входом блока сравнения, второй регистр,первый вход которого соединен с первым выходом второго блока памяти , выход первого регистра соединен со вторым входом второго блока памяти[2].Closest to the proposed is a device for selecting information, containing a series-connected first register, a first memory unit and a second memory unit, a synchronization unit connected to the first register and the first memory unit, a comparison unit, the first input of which is connected to the first output of the second memory unit, the first output with the first input of the encoder, the second output with the second input of the encoder, a block of counters, the first and second inputs of which are connected respectively with the first and second outputs of the second memory block, the output is with the first input of the comparison unit, the second register, the first input of which is connected to the first output of the second memory unit, the output of the first register is connected to the second input of the second memory unit [2].

Недостатком известных устройств является низкое быстродействие.A disadvantage of the known devices is the low speed.

Цель изобретения - повышение быст 5 родействия устройства.The purpose of the invention is to increase the speed of the device.

Поставленная цель достигается тем, что в устройство введены последовательно соединенные первый элемент НЕ, первый элемент И и счет10 чик, второй элемент НЕ, второй и третий элементы И, распределитель импульсов, элемент ИЛИ и третий блок памяти, первый и второй выходы которого соединены соответственно с первый выходом распределителя им15 пульсов и первым выходом шифратора, первый выход - со вторым входом второго регистра, второй выход - со вторьм входом блока сравнения, третий выход которого соединен со вхо20 дем первого элемента НЕ и первым входом второго элемента И, второй вход которого соединен со вторьм выходом распределители импульсов, вторьм входом первого элемента И и первые входом третьего элемента И, второй вход которого соединен с выходом первого элемента НЕ, третий вход - со вторыл выходом шифратора и входом второго элемента НЕ, выход которого соединен с третьим входом первого элемента И, выход которого соединен с первым входом распределителя импульсов, второй вход которого соединен со вторым выходом второго блока памяти и другим входом счетчика, выход которого соединен с третьим входом шифратора, выход второго элемента И соединен с третьим входом второго регистра и первым входом элемента ИЛИ, второй вход которого соединен с выходом третьего элемента И, выход - с третьим входом второго блока памяти.This goal is achieved by the fact that the first element NOT, the first element AND and the counter 10, the second element NOT, the second and third elements AND, the pulse distributor, the OR element and the third memory block, the first and second outputs of which are connected respectively to the first is the output of the distributor of 15 pulses and the first output of the encoder, the first output is with the second input of the second register, the second output is with the second input of the comparison unit, the third output of which is connected to input 20 of the first element NOT and the first input the second element AND, the second input of which is connected to the second output of the pulse distributor, the second input of the first element And and the first input of the third element And, the second input of which is connected to the output of the first element NOT, the third input - the second encoder output and the input of the second element NOT, the output of which is connected to the third input of the first element And, the output of which is connected to the first input of the pulse distributor, the second input of which is connected to the second output of the second memory unit and another input of the counter, the output of which is connected nen to the third input of the encoder, the output of the second AND gate connected to the third input of the second register and the first input of the OR gate, a second input coupled to an output of the third AND gate, the output - to the third input of the second memory block.

На чертеже Представлена блок-схема предлагаемого устройства.The drawing shows a block diagram of the proposed device.

Устройство содержит первый регистр 1, первый блок 2 памяти, второй блок 3 памяти, третий блок 4 памяти, блок 5 сравнения, блок 6 счетчиков, второй регистр 7, первый элемент НЕ 8, первый элемент И 9, счетчик 10, распределитель 11 импульсов, второй элемент НЕ 12, третий элемент И 13, шифратор 14, второй элемент И 15, элемент ИЛИ 16, блок 17 синхронизации.The device comprises a first register 1, a first memory unit 2, a second memory unit 3, a third memory unit 4, a comparison unit 5, a counter unit 6, a second register 7, a first element NOT 8, a first AND element 9, a counter 10, a pulse distributor 11, the second element is NOT 12, the third element AND 13, the encoder 14, the second element AND 15, the element OR 16, block 17 synchronization.

Устройство работает следующим образом.The device operates as follows.

Перед началом работы производится загрузка программ предварительного и полного выбора соответственно в первый и третий блоки 2 и 4 памяти.Before starting work, programs of preliminary and complete selection are loaded into the first and third blocks 2 and 4 of the memory, respectively.

Поток измерительной информации поступает со входа устройства на вход первого регистра 1. Каждое информационное слово сопровождается индексом (канала и синхронизирующим сигналом, который поступает на вход блока 17 синхронизации. Сигнал с выхода этого блока поступает на синхронизирующий вход первого регистра 1, который обеспечивает прием входных данных и их буферизацию до момента поступления следующего слова. С выхода первого регистра 1 данные поступают на информационный вход второго блока 3 памяти, причем индекс данных также поступает на адресный вход первого блока 2 памяти в качестве адреса ячейки, в которой хранится запись о выборе информации с данным индексом. При поступлении сигнала от блока 17 синхронизации на управляющий вход первого блока 2 памяти обеспечивается считывание данных выбора. При наличии в записи указателя выбора на управляющем выходе первого блока 2 памяти формируется сигнал приема данных во второй блок 3 памяти.The flow of measurement information comes from the device’s input to the input of the first register 1. Each information word is accompanied by an index (channel and a synchronizing signal that goes to the input of the synchronization block 17. The signal from the output of this block goes to the synchronization input of the first register 1, which provides input data and their buffering until the next word arrives. From the output of the first register 1, the data is fed to the information input of the second memory unit 3, and the data index also goes to the address input of the first memory block 2 as the address of the cell in which the record about the selection of information with this index is stored.When a signal from the synchronization block 17 is received at the control input of the first memory block 2, the selection data is read in. If there is a selection pointer in the record on the control output the first memory unit 2, a data reception signal is generated in the second memory unit 3.

При этом данные с выхода первого регистра 1, а также данные, содержащиеся в записи выбора (признак наличия внешнего коммутатора и его условный номер), поступают во второй блок 3 памяти. В этом блоке считывание первого слова производится непосредственно после момента переключения,, а считывание последуюших слов обеспечивается по запросам, поступающим от элемента ИЛИ.16При считывании из второго блока 3 памяти измерительные данные поступают на вход второго регистра 7, индекс канала измерительных данных поступает на вход блока 5 сравнения, а условный номер коммутатора, признак наличия внешнего коммутатора, их данные о синхронизации внешних коммутаторов, маркер цикла и маркер ламели поступают на вход блока 6 счетчиков.In this case, the data from the output of the first register 1, as well as the data contained in the selection record (a sign of the presence of an external switch and its conditional number), are received in the second memory unit 3. In this block, the reading of the first word is carried out immediately after the moment of switching, and the reading of the following words is provided upon requests from the OR element.16 When reading from the second memory block 3, the measurement data is fed to the input of the second register 7, the channel index of the measurement data is fed to the input of the block 5 comparison, and the conditional number of the switch, a sign of the presence of an external switch, their data on the synchronization of external switches, a loop marker and a lamella marker are received at the input of block 6 counters.

Блок 6 счетчиков содержит m счетчиков по числу участвующих в выбираемом потоке коммутатора, а также схемы для выбора входов и выходов соответствующего счетчика в соответствии с номером коммутатора, указанным в программе предварительного выбора.Block 6 counters contains m counters according to the number of participants involved in the selected flow of the switch, as well as circuits for selecting the inputs and outputs of the corresponding counter in accordance with the number of the switch specified in the pre-selection program.

При поступлении с выхода второго блока 3 памяти условного номера коммутатора и признака наличия внешнего коммутатора обеспечивается выбор соответствующего счетчика блока 6 счетчиков, состояние которого изменяется по сигналу чтения второго блока 3 памяти и при наличии данных о прохождении маркера коммутатора или маркера ламели-;· коммутатора. При наличии всех упомянутых данных соЬтвет- ствующий счетчик изменяет.свое состояние. При этом на выход блока 6 счетчиков поступает код состояния счетчика, соответствующий номеру ламели, на которой находится коммутатор в момент прохождения данного канала. Код с выхода блока 6 счетчиков также поступает на вход блока 5 сравнения. Код индекса канала измерительных данных и код номера ламели на входе блока сравнения образуют полный текущий адрес измерительных данных.Upon receipt from the output of the second block 3 of the memory of the conditional number of the switch and the sign of the presence of an external switch, the corresponding counter of the block 6 of counters is selected, the state of which changes by the read signal of the second block 3 of the memory and if there is data on the passage of the switch marker or the lamella marker; In the presence of all the mentioned data, the corresponding counter changes its state. At the same time, the counter status code corresponding to the number of the lamella on which the switch is located at the moment of passage of this channel is received at the output of block 6 of counters. The code from the output of block 6 counters also enters the input of block 5 comparison. The index code code of the measurement data channel and the lamella number code at the input of the comparison unit form the full current address of the measurement data.

Для выполнения выбора информации дальше осуществляется поиск в третьем блоке 4 памяти заданного адреса, соответствующего текущему адресу измерения. Поиск ведется методом последовательного деления адресов третьего блока 4 памяти пополам, при этом шифратор 14 обеспечивает последовательное формирование адресов третьего блока 4 памяти для обращения. Сигнал о выполнении чтения с управляющего выхода второго блока 3 памяти поступает на входы счетчика 10 и распределителя 11 импульсов, обеспечивая сброс счетчика 10 состояний и запуск распределителя 11 импульсов. После сброса счетчика 10 шифратор 14 формирует начальный адрес поиска, который поступает на адресный вход третьего блока 4 памяти. При этом распределитель 11 импульсов формирует сигнал запуска считывания третьего блока 4 памяти. При считывании указанного блока заданный адрес измерительных данных с его выхода поступает на вход блока 5 сравнения, вторичный ин деке поступает на вход второго регистра 7. При равенстве адресов с зыхода· блока 5 сравнения поступает сигнал на вход первого элемента НЕ 8 и на вход второго элемента И 15, а сигналы неравенства поступают на входы шифратора 14 адреса.To carry out the selection of information, a search is performed in the third memory block 4 for a given address corresponding to the current measurement address. The search is conducted by sequentially dividing the addresses of the third memory block 4 in half, while the encoder 14 provides a sequential formation of the addresses of the third memory block 4 for circulation. The signal about reading from the control output of the second memory unit 3 is fed to the inputs of the counter 10 and the pulse distributor 11, providing a reset of the state counter 10 and the start of the pulse distributor 11. After resetting the counter 10, the encoder 14 generates the initial search address, which is received at the address input of the third memory block 4. In this case, the pulse distributor 11 generates a read start signal of the third memory unit 4. When reading the specified block, the specified address of the measurement data from its output goes to the input of the comparison unit 5, the secondary index goes to the input of the second register 7. If the addresses from the output · of the comparison unit 5 are equal, the signal goes to the input of the first element NOT 8 and to the input of the second element And 15, and the inequality signals are fed to the inputs of the address encoder 14.

Затем с выхода распределителя импульсов поступает сигнал на входы первого элемента И 9, третьего элемента И 13 и второго элемента И 15....Then, from the output of the pulse distributor, a signal is supplied to the inputs of the first element And 9, the third element And 13 and the second element And 15 ....

В случае равенства адресов изме- ¹рительных данных, текущего и заданного, на выходе второго элемента И 15 формируется сигнал выбора, который поступает на второй регистр 7, разрешая прием измерительных данных и 15 соответствующего вторичного индекса. Кроме того, сигнал выбора через элемент ИЛИ 16 поступает на управляющий вход второго блока 3 памяти, выполняя считывание следующего ело- 20 ва. В случае неравенства адресов формируется сигнал на выходе первого элемента И 9, который изменяет состояние счетчика 10 на 1 и производит запуск распределителя 11 импуль- 25 сов для организации следующего этапа поиска, выполняемого аналогично описанному ранее.In the case of equality of the addresses ^{of the} measuring data ¹ , current and specified, the output of the second element And 15 generates a selection signal, which is fed to the second register 7, allowing the reception of measuring data and 15 of the corresponding secondary index. In addition, the selection signal through the OR element 16 is fed to the control input of the second memory unit 3, reading the next tree 20. In the case of an inequality of addresses, a signal is generated at the output of the first element And 9, which changes the state of the counter 10 to 1 and starts the pulse distributor 11 to organize the next search stage, which is performed similarly to that described earlier.

Предлагаемое устройство позволяет производить выбор и переиндексацию измерительных данных с производи(Тельностьюдо 20 тыс. измерений в секунду при информативности входного поиска данных, равной 500 тыс.The proposed device allows the selection and reindexing of measurement data from production (with a capacity of up to 20 thousand measurements per second with the information content of the input data search equal to 500 thousand

ΛΛ

Claims

The invention relates to ke and computing and is intended to select information. A device for selecting information is known, comprising an input register, a comparison unit, a drive and an address. Closest to the proposed. is a device for selecting information containing serially connected first register, first memory block and second memory block, synchronization block connected to the first register and first memory block, comparison block, the first input of which is connected to the first output of the second block memory, the first output with the first input of the encoder, the second output with the second input of the encoder, the counter block, the first and second inputs of which are connected respectively to the first and second outputs of the second memory block, the output from the first input of the comparison block, Torah register, a first input coupled to the first output of the second block of memory in the course of the first register is coupled to a second input of the second block memory 21. A disadvantage of the known devices is low speed. The purpose of the invention is to improve the speed of the device. The goal is achieved by the fact that the first element NOT, the first element AND and the counter, the second element NOT, the second and third elements AND / pulse distributor, the OR element and the third memory block, the first and second outputs of which are connected to the first output of the pulse distributor and the first output of the encoder, the first output to the second input of the second register, the second output to the second input of the comparator unit, the third output of which is connected to the input of the first element NOT and the first input the house of the second element And, the second input of which is connected to the second output of the pulse distributor, the second input of the first element And and the first input of the third element And, the second input of which is connected to the output of the first element NOT, the third input - to the second output of the encoder and the input of the second element NOT the output of which is connected to the third input of the first element I, the output of which is connected to the first input distributes a body of pulses, the second input of which is connected to the second output of the second memory block and another input of the counter, the output of which is connected nen with a third input of the encoder, a second yyhod the element and connected to the third input of the register and W cerned SH1I first input element, the second input of which is conn nen yield a third AND gate, the output - to the third input of the second memory blo ka. The drawing is a block diagram of the device. The device contains the first register 1, the first memory block 2, the second memory block 3, the third memory block 4, the comparison block 5, the counters block b, the second register 7, the first element is NOT the first element AND 9, the counter 10, the distributor 11 pulses the second element is NOT 12, the third element is AND 13, the encoder 14, the second element is AND 15, the element OR 16, the block 17 of synchronization. The device works as follows. Before starting work, the preliminary and full selection programs are loaded into the first and third blocks 2 and 4 of memory, respectively. The flow of measurement information comes from the device input to the input of the first register 1. Each information word is accompanied by a Channel index and a synchronization signal that goes to the input block 17 synchronization. The signal from the output of this block enters the synchronization input of the first register 1, which ensures the reception of input data and their buffering until the next word arrives. From the output of the first register 1, the data is fed to the information input of the second memory block 3, and the data index is also fed to the address input of the first memory block 2 as the address of the cell in which the record about the selection of information with the data index is stored. When a signal is received from the synchronization unit 17, the selection input is read to the control input of the first memory unit 2. When the selection pointer is present in the record, a data reception signal is formed at the control output of the first memory block 2 in the second memory block 3. I In this case, the data from the output of the first register 1, as well as the data contained in the selection record (, a sign of the presence of an external switch and its conditional number), are fed to the second memory block 3. In this block, the first word is read immediately after the switch's switch, and subsequent words are read upon requests from the OR element. 16. When reading from the second memory block 3, the measurement data is fed to the input of the second register 7, the channel index of the measurement data arrives at the turn of the comparison block 5, and the conditional number of the switch indicates the presence of an external switch, their synchronization data of the external switches, a marker cycle and lamella marker are fed to the input of a block of 6 meters. Block 6 of counters contains m counters according to the number of switches participating in a selectable flow, as well as circuits for selecting inputs and outputs of the corresponding counter in accordance with the switch number indicated in the preselection program. Upon receipt from the output of the second memory block 3 of the conditional switch number and indication of the presence of an external switch, the corresponding counter of the counter block 6 is selected, the state of which changes according to the read signal of the second memory block 3 and if there is data on the passage of the switch marker or lamella switch. If all of the above data is present, the corresponding counter changes to its own state. At the same time, the counter status code corresponding to the number of the lamella, on which the switch is located at the moment of passage of this channel, arrives at the output of block 6 of the counters. The code from the output of block 6 of the counters also enters the input of block 5 of the comparison. The index code of the channel of the measurement data and the code of the lamella number at the input of the comparison unit form the full current address of the measurement data. To perform the selection of information further, a search is performed in the third memory block 4 for a specified address corresponding to the current measurement address. The search is conducted by successively dividing the addresses of the third memory block 4 in half, while the encoder 14 ensures the sequential generation of the addresses of the third memory block 4 for access. The read completion signal from the control output of the second memory block 3 is fed to the inputs of the counter 10 and the pulse distributor 11, ensuring that the state counter 10 is reset and the pulse distributor 11 is started. After resetting the counter 10, the encoder 14 generates the search start address, which is fed to the address input of the third memory block 4. At the same time, the pulse pulley 11 generates a read start signal of the third memory block 4. When reading the specified block, the specified address of the measurement data from its output goes to the input of the comparison unit 5, the secondary index goes to the input of the second register 7. If the addresses are equal, the output of the comparison unit 5 goes to the input of the first element HE 8 and to the input of the second element AND 15, and the inequality signal is fed to the inputs of the address encoder 14. Then, from the output of the pulse distributor, a signal is fed to the inputs of the first element AND 9, the third element AND 13 and the second element AND In the case of equality of the addresses of the measurement data, current and specified, the output signal of the second register 7 is generated at the output of the second element I, permitting the acceptance of measurement data and the corresponding secondary index. In addition, the select signal cher element OR 16 is fed to the control input of the second memory block 3, reading the next word. In the case of address inequality, a signal is generated at the output of the first element AND 9, which changes the state of the counter 10 by 1 and triggers the pulse distributor 11 to start the next stage of the search, performed in the same way as previously described. The proposed device allows selection and re-indexing of measurement data with a production of up to 20 thousand measurements per second with an information content of an input data search of 500 thousand. Formula of the invention A device for selecting information containing serially connected first register, first memory block and second block memory unit, a synchronization unit connected to the first register and the first memory unit, a comparison unit, the first input which is connected to the first output of the second memory unit, the first output with the first input the encoder, the second output with the second input of the encoder, a block of counters, the first and second inputs of which are connected respectively to the first and second outputs of the second memory block, the output to the first input of the comparison unit, the second register, the nepBbdt input of which is connected to the first output of the second the memory block, the output of the first register is connected to the second input of the second memory block, characterized in that, in order to increase the speed of the device, the first element NOT, the first element AND and the counter, the second element H are entered into it E, the second and third elements AND, the pulse distributor, the OR element and the third memory, the first and second outputs of which are connected respectively to the first output of the distributor pulsiosis and the first output of the encoder, the first output to the second input of the second register, the second output to the second input comparison unit, the third output of which is connected to the input of the first element NOT and the first, the input of the second element And, the second input of which is connected to the second output of the pulse distributor, the second input of the first element And and the first input of the third element I, the second input of which is connected to the output of the first element NOT, the third input to the second output of the encoder and the input of the second element NOT, the output of which is connected to the third input of the first element I, the output of which is connected to the first-i input of the pulse distributor, the second input of which connected to the second output of the second memory block and another counter input, the output of which is connected to the third input of the encoder, the output of the second element AND is connected to the third inputs of the second register and the first input of the OR element, the second input of which of the connections with the output of the third AND gate, the output to a third input of the second memory block. Sources of information taken into account in the ri expertise 1. The author's certificate of the USSR 557414, cl. G 11 C 8/00, 1975.

2. USSR author's certificate in accordance with application f 2640464 / 18-24, cl. G06 F 15/20, 1975.