SU842772A1 - Interfacing device - Google Patents

Description

(54) DEVICE FOR PAIRING

 one

The invention relates to computing and can be used in multi-machine computing complexes for interfacing computers between soSoI and data transmission channels.

There are known interfacing devices containing a buffer memory, which includes a register, groups of information input elements and groups of information output elements, an information input distributor, an information output distributor, a register of tags, an adder, a comparison circuit, registers. constants, control node 1.

The disadvantage of these devices consists in large hardware costs. The closest to the proposed technical essence is the interface device containing a random access memory with a group of elements AND by the number of bits of the shift registers, the reversing clock distributor, the delay element, the trigger, the shift pulse generator , the first inputs of the M-th group of elements I are connected to the M-th discharge of the input bus, the outputs of the elements AND are connected to the same-named bits of the M-th shift register.

the second inputs of the elements AND of the same-named bits of all groups are connected to the corresponding outputs of the reversing clock distributor, the first input of which is connected to the trigger output and the input of the shift pulse generator, the output of which is connected to the shear bus, the second input of the reversing clock distributor

0 is connected to the input synchronization bus and one of the inputs of the delay element, the second input of which is connected to the synchronization bus, and the output is connected to the first trigger input, the second input

5 which is connected to the output synchronization bus. In this device, the input code is fed to the inputs of the elements And, the second inputs of which are controlled by signals from the outputs of the reversing

0 distributor The shift of the reversing spreader to the right is performed by the input synchronization signal after the end of the recording to the corresponding register bit of the input code.

5 The output of information comes from the last bits of the shift registers and is accompanied by the output synchronization signal, which is fed to the trigger input. Trigger generates a signal

Claims (2)

0 shift to the left for the reversible distributor and starts the driver of shift pulses, which forks the signal shifting the information recorded in the shift registers, one bit to the right. Eliminating uncertainty when signals coincide. Synchronization of input and synchronization of the driver is carried out by a delay element, which synchronizes with the synchronization signal and does not pass the signal. Synchronization of input to the trigger input at the moment of signal synchronization of output 2. The disadvantage of this device is the low rate of information exchange from - due to the impossibility of combining write and read operations, the reliability of information transmission is low, since the absence of an I / O lock can lead to Failure to register and to receive false information by the receiving machine, as well as the complexity of the device due to the need to create special synchronization signals. The purpose of the invention is to increase the fastness and reliability of information transfer. The goal is achieved by the fact that in the device containing the memory block, executed shift registers, reversing valve and delay element, and the information outputs of the shift registers are corresponding to the information outputs of the device, four AND-NOT elements are introduced, the AND element and the additional trigger the bit of the reverse. distributor, and the information inputs of the shift registers are the corresponding information inputs of the device, the inputs of the synchronization of the shift are connected to the inputs of the synchronous of the reversing distributor and the trigger of the additional discharge of the reversing distributor and the output of the first NAND element, and the inputs 15 of the write synchronization are connected to the input synchronization input of the device, the synchronization inputs of the recording of the reversible distributor and the trigger of the additional discharge of the reversing redeterminer and the first input of the second element -NO, the second input connected to the first inputs of the first and third elements of the NAND and the syphonization input of the device output, controlling the input of the register bits of the connectors The information outputs of the last discharge and the control input are connected to the information input and the control input of the additional discharge trigger of the reversing distributor, which controls the input connected to the output of the fourth element AND –NE, first the input of which is connected to the output of the third NAND element, the second input of the first NAND element and through the delay element to the third input of the NAND element, output one connected to the second inputs of the fourth and third elements IS-NOT, the output of which and the control output of the reversing distributor are connected respectively to the first and second inputs of the element I, the output of which is the output of the output resolution of the device, the information output of the additional trigger of the reversing distributor is connected to output permit device input and. information input reversing distributor. The drawing shows the block diagram of the device. The device contains a block of 1 memory on the registers 2 shift, reversing valve 3, trigger 4 additional discharge reversing valve 3, second 5, first b, third 7 and fourth 8 AND-NOT element, element 9, delay element 10, information inputs 11 and the device outputs 12, the inputs for enabling the input 13 and the device output 14, the inputs for input synchronization 15 and 16. The device works as follows. Before starting, all the bits of the reversible distributor 3, except for the first, are in the zero state, and in the first record, therefore, the control inputs of the first bits of the registers 2 are given a logic level that allows information to be written into these bits. inputs, to the control inputs of all the other pJl3p registries 2 with outputs jje. version 3 of the distributor, a logical level of O is available, allowing information to be shifted, but prohibiting recording by information inputs. From the output of the additional (last) discharge of the reversing distributor 3 (flip-flop 4), the output 13 sends a signal to the transmitting machine, disrupting the input of information into the device. The zero-level signal from the zero-output inverse output (control output) is reversible; the distributor 3 through the And 9 element on output 14 prohibits the output of information to the receiving machine. The input 15 from the transmitting machine receives a logic level O, therefore, at the output of NAND 5, the delay element 10 and at the second and third input of the element NID there are levels. At the input 16 of the receiving machine, a level is applied. As a result, the output of the element IS-HE 6 has a level Q, which is fed to the input of the element AND-HE 8, providing at its output and at the control inputs of the bits of the reversing distributor the level allowing the recording of information in them by information entry. The zero level signal from the output of the NAND 6 element is also fed to the input of the NAND 7 element and provides a logic level at its output. A single impulse synchronization input from the transmitting machine passes to the input element AND-NOT 5, does not change the level at its output, since the second input of the element AND-NOT 5 is fed level R. On the rear edge of the input synchronization pulse, coming to the synchronization inputs C2 for recording, information is recorded in the first bits of registers 2, since the control inputs contain a level that allows recording and is shifted to the left in the reversing distributor 3, since the control inputs of all its bits, from the output of the element AND-NOT 8 level is given. writing a record of information. Therefore, after the termination of the synchronization pulse, the first bit of the reversible distributor 3 enters the state and a single signal from its inverted output goes to the output of element 9, since a single level signal from the output of element 9 acts on the other input of element 9 - NO 7 Thus, after recording, the code in the first bits of registers 2 from the transmitting machine from the output of element 9 to the receiving machine is given a signal permitting the output of information and from the first bit of the reversing distributor 3 is shifted a second time. The row from the output of which the unit level is fed to the control inputs of the second bits of registers 2. After the end of the second input synchronization pulse, the code is written to input 11 to the second bits of registers 2, and, recorded in the second bit of the reversing distributor 3, is shifted into its third bit. Therefore, when the device receives each parallel code, the input synchronization signal shifts 1 in the reversing distributor 3 to the left by one bit. This happens before the code is written in the last bits ISTRY 2 when i ub penultimate discharge distributor sdvigaetsd reversible in its additional bits. In this case, the signal is removed razraieni input to you during 12 that sviDetels tvuet Zapolle nenii of all registers 2 1 memory block. The receiving computer, with the presence of a signal. The output resolution at output 14 from the output of element 19 can start reading information from registers 2 of block 1 at any time by sending a zero-level synchronization pulse to input 16. This impulse arrives at the input of the NAND element 6. On the leading edge of this impulse, the parallel code is read from the first bits of the registers 2. If there is no difference in time with the impulse synchronization of the input impulse, the output synchronization impulse forms at the output of the NES element 6 equal duration to it, which is fed to the clock synchronization inputs C1 of each bit of all registers 2 and reversing distributor 3. Therefore, on the falling edge of the pulse from the output of the AND-HE element 6, information is shifted to one bit to the right in all filled bits of registers 2, since the control inputs of these bits have a zero level signal from the outputs of the reversing distributor 3, which allows the shift to the right. At the same time, a single level signal is received from the output of the AND-NOT element 5. Therefore, the zero-level signal is generated at the output of the elegant agent IS-NOT 8, which is not fed to the control inputs of all the bits of the reversing distributor 3, thereby shifting it to the right. the signal from the output of the first element AND-NOT b passes the shift 1 to the previous discharge of the reversing distributor. The termination of the zero-level signal at the output of the NAND 8 element occurs after the end of the pulse at the output of the K-tiB element b by the delay time of the signal by the NAND element 8, which ensures a reliable shift to the right. Thus, the mismatch of the pulses Synchronization of the input and Synchronization 0 of the shdvod pushes 1 in the reversible distributor 3 and the shape in the registers 2 one step to the right until it is in the perch: 1st bit of the reversible distributor. In this case, at the output of AND 9, a level appears that removes the output resolution signal at output 14. In the case of coincidence in time of the pulses for synoning the output and synchronizing the input at the output of the element AND-NOT 5, a zero level signal is generated, which is fed to the second input of the element AND-NOT 6, and after the time determined by the delay element 6, the third input of the element AND - “E b. At the same time, the zero-level signal is fed to the input of the NANDI element, 8, maintaining a single level at its output, which is sent to the control inputs of each reversing distributor, thereby allowing the left-shift mode. The delay time in the delay element b is selected as a function of the transition process time in registers 2 and in the reversing distributor Zi of the signal duration Input input 15 synchronization. It is clear that in the case of pulse timing input synchronization and output synchronization the rear negative front of the output signal The AND-NE element 6 is formed no earlier than through the delay time of the element 10 after the end of the input synchronization pulse. Therefore, in this case, information is recorded independently from the transmitting machine into the corresponding bits of registers 2 and information is output from the first bits of registers 2 to the receiving machine (along the front of the output synchronization pulse). At the same time, on the falling edge of the synchronization of the input, a shift 1 occurs one digit to the left in the reversing distributor 3 and after a time longer than the delay time on the element 10, the falling edge of the signal at the output of the NAND element 6 is formed, over which the shift occurs information in registers 2 and in reversing distributor 3 one bit to the right. If the output synchronization impulse ends before the signal from the output of the delay element 10, after it ends, the output signal of the NAND 7 generates a zero level signal which, through the AND 9 element, removes the output resolution before the signal ends at the output element delays 10. This avoids the re-output of the same information. Thus, the use of the proposed device allows the exchange of information at any correlation of the speeds of the transmitting and receiving machines. The speed of the device is determined by the speed of the applied element base. To function, the device does not require the creation of special synchronizing pulses, which allows to match universal output signals from industry, which, as a rule / when outputting information, give out only one impulse of information tracking. In addition, the device | Provides high reliability of undistorted information transmission with relatively small complexity and the amount of equipment. Claims An interface device comprising a memory unit configured in the shear registers, a reversing distributor and a delay element, and; information outputs of the shift registers are the corresponding information outputs of the device, characterized in that, in order to increase speed, four AND-NOT elements are introduced into it, the AND element and the trigger of the additional discharge of the reversing distributor, and the information inputs of the shift registers are the corresponding information inputs devices, shift synchronization inputs are connected to synchronization inputs of the reversing distributor and the trigger of the additional discharge of the reversing distributor and the output of the first element AND-N and the synchronization outputs of the recording are connected to the input synchronization input of the device, the synchronization inputs of the recording reversing distributors trigger additional discharge reversing distributor and the first input of the second element IS-NOT, the second input connected to the first inputs of the first and third elements NAND and the device output synchronization input, the control inputs of the shift register bits are respectively connected to the information outputs of the same name reversing distribution bits the body, the information output of the last bit and the control input of which are connected respectively to the information input and control input of the trigger of the additional discharge of the reversing distributor, the control input of the fourth element AND-NOT connected to the output of which is connected to the output of the third element AND-NOT , The SECOND input of the first element NAND and through the delay element k., The third input of the first element NAND, the output connected to the second inputs of the fourth and third elements NAND, the output of which is yn the equal output of the reversing distributor is connected respectively to the first and second inputs of the AND element, the output of which is the output output of the device; the information output of the additional discharge trigger of the reversing distributor is connected to the output enable input of the device and the information input of the reversible distributor. Sources of information / taken into account during the examination 1. USSR author's certificate 602934, cl. G About F 3/04, 1975. 2. USSR author's certificate number 401999, cl. G 06 F 13/02, 1971 (prototype) .; Sync 1t Synz1rvn "9v (chi fitloSff iSada