SU842617A1 - Frequency-to-code iteration converter - Google Patents

Description

The invention relates to e-hectronic circuits o6i: iero assignment and is intended for use: -: and in ixrovic systems, an automatic - on the display.

There is a known re speci l j ta-code (PChK) consisting of a pulse generator, a laziness circuit, a counter, a register, and a shared frequency / n frequency. Frequency conversion; in the code of the program interface by counting pulses of an impulse generator for the time interval between two pulses of the frequency being converted: l.

A disadvantage of the known device is that expanding the range of the frequency to be converted leads to a decrease in speed and an increase in the complexity of the device.

The purpose of the invention is to expand the range of convertible frequencies by lei: not speed.

The goal is achieved by the fact that in a frequency-code converter containing a reversible counter, the first control output of which is connected to the first input of the control unit, a pulse generator, the output of which is connected to

Control Yshog-, lt: ra. B: 1 is a splittable frequency divider: - ;, BHXOZ; which is connected to the second / input of the chArElek block, entered: follower -: -: a connect: -; intelligent smart: -kitel, selector kgdzor and naka :: livayutsy adder, prkchem to: -1; go: reverse counter very: to :: epso; to the group of entries of the corner; s: o: “itel, - the second group Bxojiiog to about 7 o r about with about e d and nds ;;:: -: vayu: ;; his favorite .tselitel: g : and the entrances are self-imposed.;. with:;: other constants issry the inputs of the control unit for the SC:. uyche: -: s to the second control output of the reversible counter and for the input: -: accumulating the cyNMaTopa correspondingly, the first:, the second and the third

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Claims (1)

m, rank i, has a chain with the quotient of the number 1/2, and;;, l of all f, entering into a valuable segment, the stability condition is satisfied. Thus, the output code of the multiplier 3 is m. This code through the selector 4 is fed to the accumulating cy.lmatop 5 1de at the end of the cycle is added to the code of the previous result F As a result, at the end of the measuring cycle, the output code P. -PF (M-foF ,, r, M) With the arrival of the next pulse, the cycle repeats. If the GO counter 2 counts the NI pulses before the measuring interval ends. When n + 1 pulses arrive, during 0, a signal that tripper 8 triggers, as a result, element 3 will close and the divisions of the bodies will begin to flow through element 12 the summing input of counter 2, Thus, in this mode, the contents of counter 2 at the end of the measurement:; ikla is equal to ff M - N Logs Iecca and the unit from the output of three heras enters the input of the accumulating co.dmator, as a result from the P code in with According to formula 11, With large jump abrupt f, the number of pulses V may exceed 2N, i.e. the number of pulses arriving at counter 2, after triggered, three hera 8 may exceed N. At the same time, the counter may go to the zero state and its readings will not correspond to the error value. To prevent this, the overflow output of the counter is connected to the output of the element 12, as a result of which the latter closes and the pulse counting stops. The sum of the torus 5 continuously generates a difference signal between F and the code B at the output of the selector 4. If the difference is negative, a logical output appears at the output P of the transfer of adder 5. If Fj F (trigger 8 cocked and at some point in time F 1 - B becomes negative, trigger 10 through AND 1 is cocked at the output of selector 4. N, which appears the code of number 3, is chosen so that the difference code could not become negative, when this is subtracted from F, claims 1. An iterative frequency-code converter containing a reversible counter, the first control output of which is connected to the first input of the control unit, a pulse generator, the output of which is connected to the control input of the controlled dividerFrequency, the output of which is connected to the second input of the control unit /; Eni, characterized in that, in order to expand the frequency conversion range and increase speed, it introduces serially connected multiplier, code selector and accumulator with mmator, and the reversible counter outputs connected: the first group of inputs of the i.-southernizer, the second group of inputs of which is connected to the inputs of the accumulating adder and the inputs of the controlled frequency divider, one group of inputs of the code selector is connected to the; . Rd and fourth inputs sound control unit: CNI connected to the second output upoavl yuschemu down counter and the output from the accumulator; .- mmatora match: -: but the first, second and Treu n p l e n n o d; luche to Bkchitayughdemu, cyN i: n-n-; c: .y nr; -: o ;; a-up-and-down counter,; ьг ;;: ta: -n: aiy and summator coe. ;; -: i t.iib with fourth and fifth: xc;:.; m ;; Blogs Manage ;; I; ;;; Proob Zazovagel according to claim 1, about T l and -; a y u and with the fact that y; times ;; e; ; and so ;; e; y -:.: it is three RS trigger, tr; h And echement for ,, pr1; than K-vksd; all rs-tr} of the gerop are united and connected to the zykhod 1leme that delay, first., input; om of the first element And li tuet:: m; output of the control unit, the first and second ::. ohg-; 1 of which are the output; - the second and third elements And, respectively, the fourth output of the block: /: - the output is connected to the direct output of the rms RS flip-flop, the first input / of the second element And the second input of the first element And, the output of which is connected to the S-input of the second RS-trigger, the output of which is the output of the control unit, the fifth output of which is connected to the output of the first RS-trigger and the input of the delay element, the first input, the control unit is connected to the S-input of the third RS-flip Serra, the inverse output is connected to the first input of the third element And, the second input of which is connected to the second inputs of the second element And and the control unit, the third input of which is connected to the third input of the third element K, the fourth input