SU1033983A1 - Digital phase meter - Google Patents

Abstract

The DIGITAL PHASOMETER containing the synchronizer is connected. boscopic and analog-to-digital converters connected to the synchronizer, adder, connected. with the output of the register unit and connected via the register unit to two multipliers connected directly to the storage unit, and through adders with accumulators with the calculator, the output of the synchronizer is connected to the input of the storage unit, in order to improve the measurement accuracy phase shifts at the impact of the SRI of a spectrum-centered disturbance, a multiplexer, a clock pulse generator, three counters, two elements And a pulse generator, a trigger, a division block, a subtractor, a decoder are entered into it. an ator and a start-up unit, the multiplexer is connected to an analog-digital converter, an adder and a register block, a clock generator is connected to an analog-digital converter, the first counter is connected to a multiplexer, a clock generator and a block of registers, the synchronizer is connected to serially connected first the element and the counter, the division block (L to the subtracting counter, the third counter, the decoder connected to the adder, and to the serially connected second element I, to the trigger, the start-up block, the trigger is connected to the third counter, subtracting the count- s; chick -. with the start-up unit and the second element And, the pulse generator - with the first element I. from 00 to 00 with

Description

Of course, brevity is related to electrical measuring equipment and can be used in the development of high-precision digital phase meters operating under conditions of spectrum-centered interference.

A phase meter is known that contains a stroboscopic converter, an analog-to-digital converter, two multipliers, two accumulators with memory capacitors, a permanent storage unit, and a function calculation unit in /. I synchronizer and formator. :. The disadvantage of this phase meter is low measurement accuracy due to interference.

The closest to the proposed technical essence is a digital phase meter containing sequentially connected strobe and analog-to-digital converters, a synchronizer, a storage unit, two multipliers connected to the storage unit and through adders from the accumulator to the calculator, an adder connected to the analog-digital converter and the synchronizer, serially connected register block and register control block connected to the synchronizer, the output of the register block with One with: E and peromnozhitel summatoromS2.

A disadvantage of the known device is a large error, under the condition that the phase meter input together with the measured signal is concentrated, the spectrum is disturbed.

The purpose of the invention is to improve the accuracy of measurement of phase shifts under the influence of spectrum-concentrated interference.

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This goal is achieved by the fact that a digital phase meter containing a synchronizer, connected by a stroboscopic and analog-digital converters connected to a synchronizer, an adder connected to the output of a block of registers and connected through a block of registers to two multipliers connected directly to the memory block. and through accumulators with accumulators - with a calculator, the synchronizer output is connected to the input of the storage unit, a multiplexer, clock pulse generator, three counters, two AND elements, and erator pulses, trigger, block dividing, down counter, decoder and starter unit, wherein the multiplexer is coupled to an analog-digital converter, an adder and a register unit, a clock generator connected to the analog-to-digital converter, the first sch1etchik

connected to a multiplexer, a clock generator and a block of registers, the synchronizer is connected to the first element AND, the second counter, block

division, subtract counter,

the third counter, a decoder connected to the adder, and to the serially connected second element I, the trigger, the start-up unit, the trigger

connected to the third counter, the subtracting counter is connected to the start block. ; and the second element And, the pulse generator - with the first element I.

The drawing shows blo, K-scheme of the proposed device.

The device contains a stroboscopic transducer 1, connected via serially connected. A / D converter. 2, multiplexer 3, adder 4 and. block 5 registers with two multipliers b and 7, which are connected directly to the storage unit 8, and through adders 9 and 10 with accumulators - to the calculator 11, synchronizer G2, connected through serially connected first element I 13, second counter 14, A dividing block 1, a subtracting counter 16, a third counter 17, a decoder 18 and a first counter 19 with a generator of 20 clock pulses; a trigger 21 is connected to the second element 22 and the start block 23. The pulse generator 24 is connected to the first element And 13, the synchronizer 12 to the second element And 22, the storage unit 8 with the stroboscopic and analog-digital converters 1 and 2, the starting module 23 to the subtracting counter 16, the generator 20 clock pulses to the analog -digital converter 2, the VELs of the block 5 registers are connected to multiplexer 3 and adder 4, the first counter 19 is connected to multiplexer 3 and block 5 registers, the decoder 18 - with adder 4, the third counter 17 - with trigger 21, the second element I 22 - with subtractive counter 16.

The device works as follows. .

The first input receives the voltage with a measured phase shift, the second - the reference signal. The stroboscopic and analog-to-digital converters 1 and 2 are time-sliced and sampled according to the input signal level, so that the output of the analog-digital converter 2 shows the codes of the instantaneous values of the input signal corresponding to the reading moments, under the influence of pulses from the output of the synchronizer 12 whose period is equal to dt T / p, where T is the inbound period. gpro signal, P is the number of samples placed in one period of the input signal. The codes from the output of the analog-to-digital converter 2 pass through the mule type 3 and with the help of adder 4 they accumulate in block 5 of registers in the form of generated amounts. The entire block 5 of registers is divided into groups of registers 25-27, each group contains P registers. At the end of the accumulation process, i.e. The measurement time .T (C3 (. P®gistras of the last group) are recorded codes of instantaneous values of the input signal at P points. Count. The Hu codes of the last group of registers are sequentially read by multipliers b and 7, where they are multiplied by the trigonometric coefficients sinioi / ii and cos itu l t ,, stored in memory block 8 and called from there by synchronizer commands 12 The measurement result is calculated using the formula P. SiHiu) dt i-0, 4 ptrctt x-cosiioat where tx 2Jr / r. Decrease of error caused by spectrum-centered interference 1 is produced. by weight processing (a triangular weight function is used) .. For example, take the measurement time Tj k T. Then for the triangular weight function the weights should be as follows (k 5):: 9fi 1/2, P5 The index denotes the period number of the input signal in the measurement time, thus, the samples in the first period should be multiplied by 1 / in the second period - by 2, in the third period - by 3, etc. For large It, the weights become large, and the time spent on the multiplication operation x s - - significant. However, elimination of the multiplication operation is possible. For the triangular weighting function (the weighting functions of the first order block 5. registers must consist of two groups of registers. Note that each group contains P registers, but since in the same period everything is multiplied by a constant weight. The coefficient will be considered for one register from each GROUP. The initial state of each register 25 and 26 is zero.Labin algorithm in register 25 pij pv, +. Accumulation algorithm in register 26. Р2-Plj ± PZj ..,. The accumulated results are tabulated. Pitch: register by the end of the measurement time accumulates a value that takes into account all the samples, but each with a weight corresponding to the triangular weight function. Thus, the multiplication operation is replaced by 2 + 1 summation operations (subtraction after each A / D conversion independently of 1, i.e., the time is measured, where Z is the order of the weight function. As indicated, the number of register groups is also equal to Z +1. The clock pulse generator 20 is triggered by a pulse from the output of the analog-to-digital converter 2, corresponding to the end of the conversion of the analog value to a code. The clock pulse generator 20 generates Z + 1 pulses, which are computed by the first counter 19 for control 1f multiplexer 3 and block 5 of registers. For the example above, a clock pulse generator 20 produces two pulses. At the first pulse multiplexer. 3 connects the output of the analog-to-digital converter 2 to the input of the adder 4. A register Pi is connected to the second input of the adder 4 at this time. The result of the addition is written to that. same register. At the second clock pulse multiplex 3 connects to the adder 4, the register P2. to the second input of the adder 4 is connected at this time the register Pi. -Resummation result: Neither (or subtraction) is written into register P2. At this time, the processing cycle of a coy from the output of the analog-digital converter 2 is complementary; The decoder 18 forms the sign of the operation (summation or subtraction) produced in the adder 4. This happens in the following way. The generator 24 pulses, the first | Element-t I 13 and the second counter 14 v | are the transducer of the period of the input signal to the code, M Tfp, where fo is the pulse frequency of the generator 24 pulses. In division block 15, the operation 1ru / t is performed (the whole part of the ratio Ni, 5 / NT is equal to k, i.e. the number of input signal periods laid down during measurement. The weight function is split into two sections, during which the sign of the BI operation. () is not changed. Since the number of plots is a power of two /, this makes it easy to determine the number of input signal periods in one section by dividing the number from the output of dividing unit 15 by 2 i.e. shift and the corresponding number of bits. The number tri is transferred into subtractive counter 16 by the command of block 23. By the same command, a trigger 21 is entered, which opens the second element AND 22. The pulses from the output of synchronizer 12, following with period 4i, pass to the subtracting counter 16. The subtractive the counter 16 clears the moment fi of the end of the current segment.The number m will again be rewritten in the subtracting counter 16, and the state of the third counter 17 will increase by 1. The capacity of the third counter 17 is equal to the number of sections of the weight function, i.e. at the moment of its overflow, the measurement time will end. Thus, at the outputs of the third counter 17 there are codes. Which are converted by the decoder 18 into an operation-sign for the adder 4. / For addition, the addition operation is always used in register 25. To ensure this, use is made of locking the decoder 18, carried out in accordance with the state of the first counter 19. The operation with the other 1 and 2 does not change the structure of the device. The technical effect of the invention is determined by the filtering of the spectrum-centered interference.

Claims (1)

) A DIGITAL PHASOMETER containing a synchronizer, connected stroboscopic and analog-to-digital converters connected to a synchronizer, an adder connected. with the output of the block of registers and connected through the block of registers to two multipliers connected directly to the storage block In order to increase the accuracy of measuring phase shifts under the influence of noise concentrated over the spectrum, a multiplexer, a clock generator, three counters, two elements and a pulse generator, a trigger, a division unit, a subtracting counter are introduced into it, p and a start block, wherein the multiplexer is connected to the analog-to-digital converter, the adder and the register block, the clock generator is connected to the analog-to-digital converter, the first counter is connected to the multiplexer, the clock generator and the register block, the synchronizer is connected to the first AND element in series , the second counter, the division block subtracting the counter, the third counter, the decoder connected to the adder, and to the second element And connected in series, trigger, block p hitch, the trigger is connected to a third counter, a subtracting counter with a start block and a second element And, a pulse generator - with the first element I.