SU1367128A1 - Shaper of multifrequency signal - Google Patents

Abstract

Invention m. used in measurement technology to capture frequency x-signals in the low-frequency range. The purpose of the invention is to reduce the irregularity of frequency shifts between signals in the output multi-frequency signal. The form-l contains r-1 clock pulses, counters 2 and 3, shaper 4 pulses, memory block 5, registers 6-8 memory, DAC 9-10, digital delay line II, algebraic. adder 12, controlled by inverter 13, adders 14-16; block 17 of permanent memorization and filter with (O

Description

one

The invention relates to radio engineering and communications, and can be used in measurement technology to measure the frequency characteristics of signals in the low frequency region.

The aim of the invention is to reduce the unevenness of the frequency shifts between signals in the output multi-frequency signal.

Fig. 1 shows a structural electrical circuit of a multifrequency driver; Figures 2, 3 and 4 are timing diagrams explaining the operation of a multifrequency generator; figure 5 - the spectral characteristics of the output signal

The multifrequency signal generator contains a generator of 1 clock pulses, the first and second counters 2 and 3, the driver of 4 pulses, memory block 5, the first, second and third registers 6.7 and 8 of memory, the first and second digital-to-analog converters 9 and 10, a digital delay line 11, an algebraic adder 12, a controlled inverter 13, first, second and third adders 14, 15 and 16 a permanent storage unit 17 and a low pass filter 18.

Shaper multifrequency signal works as follows.

From the generator output I clock pulses on the counting; the inputs of the first and second counters 2 and 3 receive clock pulses. During the first cycle of operation of the multifrequency signal generator, a zero address code is formed at the output of the first counter 2, and this reads information in memory block 5 from the zero cell. The information input of the second counter 3 receives the code determining its conversion factor and, accordingly, the number of time subchannels of the multifrequency signal generator. The first input of the first adder 14 receives a code defining the initial value of the function argument in the first time subchannel, and the first input of the second adder 15 receives a code defining the change of the initial value of the argument from one time subchannel to another. Starting from the second cycle of operation of the multifrequency generator, and until the appearance of a pulse at the end of the delay period from the output of the digital delay line 11,

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The first setting of the second counter 3 at the input, the first input of the first adder 14 contains a zero code value, and the first input of the second adder 15 and the information input of the second counter 3 does not change the code value. At the same time, at the output of the second register 7, when the i-ro clock pulse is applied, the initial value of the argument is formed in the i-th time subchannel (Fig. 3a). The overflow pulse of the second counter 3 (FIG. 3b) zeroed the second register 7. The principle of forming the initial value of the argument of the sinusoidal function and the signal at the output of the second counter 3 is shown in the time diagrams of FIG. 3a, b. The first input of the algebraic adder 12 receives the code of the initial value of the argument of the sinusoidal function, which is summed with the code coming from the first output of the digital delay line II. The summation result, passed without change through the controlled inverter 13, is fed to the information input of the digital delay line 1 1. Upon completion of the next delay period with the initial value unchanged in the first time subchannel arriving at the second input of the algebraic adder 12, the initial value of the argument is summed with its current value read from the output of the digital delay line 11, and the initial value of the argument becomes meaningful increments of the function argument from period to period. At the same time, a linearly increasing signal is formed at the input of the continuous memorization unit 17, consisting of samples following a delay period. When the algebraic adder 12 overflows, an overflow signal appears at its transfer pulse output, which is detected by shaper 4. From the shaper 4 output, the unit addition signal to the low-order bit goes to the second control input of the algebraic adder 12. At that, the algebraic adder 12 performs the operation A + B + 1. The controlled inverter inverts the result. The control signal from the generator 4 output together with the result of the calculation is recorded in the digital delay line 11 and in the next period the algebra and operation code changes.

from the summation operation to the subtraction operation, which is performed until the next occurrence of the overflow signal. After

This is followed by operations AB-1, and the controlled inverter 13 inverts the result obtained. In the next period, the control signal changes the operation code of the algebraic adder 12 from the subtraction operation to the summation operation. The principle of forming the argument of a sinusoidal function in one time subchannel is shown in FIG. 2a, b. In the remaining time subchannels in the delay period, the change in the value of the argument is similar (Fig. 4). The signal from the output of the block 17 of continuous memorization is fed to the input of the first digital-to-inverter converter 9 and to the second input of the third adder 16. A recirculation accumulator consisting of the third adder 16 and the third register 8 performs summation of counts of sinusoidal oscillations formed in all time subchannels within each period. Here, the code of the time subchannels is converted into one channel. The third register 8 delays a signal by one time subchannel. At the end of the operation of summing up the counts of sinusoidal oscillations of all time subchannels in each of the periods, the third register 8 is set to zero by the control signal coming from the output of the second counter 3 to the input of setting the third register 8. On the negative front of the same signal supplied to the input of the record of the first register 6 shown in fig. 3b, the information from the output of the third adder 16 is overwritten into the register 6. The signal from the output of the register 6. is fed to the input of the second digital-to-analog converter 10, and from the output of the digital-to-analog converter 10 through a low-pass filter 18 to the third output of the multifrequency signal. The principle of forming a spectrum of signals at the output of the second digital-to-analog converter 10 and at the output of the low-pass filter 18 is shown in FIG. 5a, b. Formula of invention

Shaper multifrequency signal containing consistently 28

the first counter, the memory unit and the second counter, are connected in series with the persistent storage unit and the first digital-to-analog converter, the output of which is the first output of the multifrequency signal generator, the first memory register and the second digital-analog converter, pulse generator and clock generator, sequentially connected, characterized in that, in order to reduce the non-uniformity of the frequency shifts between the signals in the output multi-frequency signal, digitally connected delay lines, an algebraic adder and a controlled inverter, the first adder, the second adder and the second memory register, the third adder and the third memory register, the output of which is connected to the first input of the third adder, and a low-pass filter, connected in series, the input of which is connected to the output of the second digital-to-analog converter, the counting inputs of the first and second counters are combined with the synchronization inputs of the second and third memory registers, the former pulses and a digital delay line and connected to the output of the clock generator, the second and third outputs of the memory unit are connected to the first inputs of the first and second adders, the second input of the first adder is combined with the second input of the algebraic adder and connected to the output of the second memory register, the output of the controlled inverter is connected to the information input of the digital delay line and to the address input of the permanent storage unit, the output of which is connected to the second input of the third adder, the output of the third the second adder is connected to the information input of the first memory register, the recording input of which is combined with the zero setting inputs of the second and third memory registers and connected to the output of the second counter, the initial installation input of the second counter is connected to the second output of the digital delay line, the third output of which is connected to the first control input of the algebraic adder, the output of the transfer pulse of the algebraic sum51367128,

The mate- rial is connected to the information input of the hebraic adder, the output of the pulse shaper house, the output of the permanent memory is the second connected to the control input of the shaper by a frequency-controlled inverter, from the control signal, and the output of the lower filter frequency - the third output shaper multifrequency signal.

the digital input of the delay line and the second control input

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Claims (1)

Multifrequency signal shaper containing sequentially soy 67128 are the first counter, the memory unit and the second counter connected in series with the memory unit ₅ and the first digital-to-analog conversion. a generator, the output of which is the first output of the multi-frequency signal shaper, a first memory register and 10 a second digital-to-analog converter, a pulse shaper and a clock pulse generator, characterized in that, in order to reduce the unevenness of the frequency shifts 15 between the signals in the output multi-frequency signal, it introduced a series-connected digital delay line, an algebraic adder and a controlled inverter, 20 series-connected first adder, W A second adder and a second memory register, a third adder and a third memory register connected in series, the output of which is connected to the first input of the third adder, and a low-pass filter, the input of which is connected to the output of the second digital-to-analog converter, the counting inputs of the first and second counters are combined with 30 inputs synchronization of the second and third memory registers, pulse shaper and digital delay line and are connected to the output of the clock generator 35 ow, the second and third outputs of the memory block are connected to by the first inputs of the first and second adders, respectively, the second input of the first adder is combined with the second input of the algebraic. the adder and is connected to the 'output of the second memory register, the output of the controlled inverter is connected to the information input of the digital delay line and to the address input 45 of the permanent storage unit, the output of which is connected to the second input of the third adder, the output of the third adder is connected to the information input of the first memory register, input 5Q records of which are combined with inputs: zeroing of the second and third memory registers and connected to the output of the second counter, the input of the initial setting of the second counter is connected 55 to the second the digital delay line, the third output of which is connected to the first control input of the algebraic adder, the output of the transfer pulse of the algebraic sum 5 1367128 motherboard is connected to the information input of the pulse shaper, the output of which is connected to the control input of the controlled inverter, with the control input of the digital delay line and with the second control input of the algebraic adder, the output of the read-only memory unit is the second output of the multi-frequency signal shaper, and the low-pass filter output -1 the third output of the shaper of a multi-frequency signal.