SU1667038A1 - Special signal generator - Google Patents

Abstract

The invention relates to radio engineering and communication technology and can be used in measurement technology to capture the amplitude-frequency characteristics of digital and analog devices, as well as to generate test signals of a special form. The purpose of the invention is to expand the field of application by independently adjusting the phase of each component of the output high-frequency signal. The special signal generator contains 1 clock pulse generator, the first counter 2, the second counter 16, the first 4, the second 5, the third 11 and the fourth 22 adders, the first 6, the second 10 and the third 12 registers, the HE 7 controllable element, the digital delay line 8 , algebraic adder 9, first 13 and second 18 digital-to-analog converters, low-pass filter 14, shaper 15 pulses, first 17, second 19 and third 21 sine memory blocks, spectral component amplitudes, spectral component phases, respectively, multiplier 20, block 3 memories Frequency of laziness. This goal is achieved by introducing the block 21 of the memory of the phases of the spectral components and the adder 22. 6 Il.

Description

The invention relates to radio engineering and communication technology and can be used in measuring technique for recording the amplitude-frequency characteristics of digital and analog devices, as well as for generating test signals of a special form.

The purpose of the invention is the expansion of the scope by independently adjusting the phase of each spectral component of the output multi-frequency signal.

In FIG. 1 shows a structural diagram of a special signal generator; in FIG. 2-5 are timing diagrams explaining the operation of the special signal generator; in Fig.6 - the spectral characteristics of the output signal for the linear law of variation of the amplitudes of the spectral components of the multi-frequency signal.

The special signal generator comprises a clock pulse generator 1, connected in series with a first counter 2, a frequency determination memory unit 3, a first adder 4, a second adder 5 and a first register 6, a controlled element HE 7 and a digital delay line 8, an algebraic adder 9. second register 10 , the third adder 11, the third register 12, the first digital-to-analog converter 13 and a low-pass filter 14, a pulse shaper 15, a second counter 16, a sine memory block 17 and a second digital-to-analog converter 18, a spec amplitudes memory block 19 component, the multiplier 20, the block 21 of the phase memory of the spectral components and the fourth adder 22.

The special signal generator operates as follows.

From the output of the generator 1 clock pulses to the counting inputs of the first 2 and second 16 counters receive clock pulses. During the first clock cycle of the special signal generator, a zero address code is generated at the output of the first counter 2. When this happens, the reading of information from block 3 of the memory from the zero cell. The code input of the second counter 16 receives a code that determines its conversion factor and, accordingly, the number of temporary subchannels of the special signal generator. The first input of the first adder 4 receives a code that determines the initial value of the argument of the function in the first time subchannel. and the second input of the second adder 5 receives the code. determining the change in the initial value of the argument from one temporary subchannel to another. Starting from the second clock cycle of the special signal generator and until a pulse appears at the end of the delay period from the output of the digital delay line 8, which is fed to the input of the initial installation of the second counter 16, the code zero is present at the first input of the first adder 4, and the second adder 5 and at the code input of the second counter 16, the code value does not change. In this case, at the output of register 6, when the Ιth clock pulse is applied, the initial value of the argument is generated in the kth time subchannel (Fig. 2a), where k is the number of the temporary subchannel, the overflow pulse of the second counter 16 (Fig. 26) resets register 6. Principle the formation of the initial value of the argument of the sinusoidal function and the signal at the output of the second counter 16 is shown in the time diagrams (Fig. 26), where η is the number of the current discrete.

The code of the initial value of the argument of the sinusoidal function is input to the fourth adder 22, with the help of which the initial value of the phase is determined by the code supplied to the other input of the fourth adder 22 from the output of the memory unit 21. The principle of changing the phase of a sinusoidal oscillation by 90 ° in one time subchannel is shown in FIG. For, b. A phase change of 90 ° occurs when a single code is supplied. From the output of the fourth adder 22, the digital code is fed to the input of the algebraic adder 9, which is summed with the code from the output of the digital delay line 8. The result of the summation, passing without change through the controlled element NOT 7, is fed to the input of the digital delay line 8. At the end of the next delay period, at an unchanged initial value in the first time subchannel supplied to the other input of the algebraic adder 9, the initial value of the argument is summed with its current value read from the output of the digital delay line 8, and the initial value of the argument acquires the meaning of incrementing the function argument from period to period. At the same time, a linearly increasing code is formed at the output of register 6, consisting of samples following the delay period. A single summation over the N periods of the initial phase code to the code of the increment of the function argument from period to period or a change in the initial phase code from the period according to the necessary law for the periods laid down in the third memory block 21 in each of the temporary subchannels leads to the necessary change in the initial phase or the necessary law of phase modulation in each of the temporary subchannels. In this case, the distribution of the initial phase codes within the period over time subchannels is determined by the code of the lower address bits of the third memory block 21 coming from the first output of the first counter 2, and the phase change from period to period is determined by the code of the higher address bits coming from the second output of the first counter 2 ( senior ranks). The conversion factor of the first counter 2 determines the number of modulation periods in phase. After the overflow of the first counter 2, the law of phase modulation is repeated.

When the algebraic adder 9 is overflowed, an overflow signal appears on its output of the transfer pulse, which is fixed by the pulse shaper 15. From the output of the pulse shaper 15, the signal of adding a unit to the least significant bit is fed to the second control input of the algebraic adder 9. In this case, the algebraic adder 9 performs the operation A + B + 1. The controlled element NOT 7 inverts the result. The control signal from the output of the pulse shaper 15 along with the calculation result is recorded in the digital delay line 8 and in the next period changes the operation code of the algebraic adder 9 from the summing operation to the subtraction operation, which is performed until the next overflow signal appears. After that, operation A-B1 is performed, and the controlled element NOT 7 inverts the result. In the next period, the control signal changes the operation code of the algebraic adder 9 from the subtraction operation to the summation operation. The principle of generating an argument of a sinusoidal function in one time subchannel with a zero code of the initial phase from the output of the third memory unit 21 is shown in FIG. 4a, b. In other time subchannels in the delay period, the change in the argument value occurs similarly (Fig. 5), where N is the number of the delay period, η is the number of the current discrete, and k is the number of the temporary subchannel.

The signal from the output of the first memory block 17 is fed to the input of the multiplier 20 of the numbers represented by a digital code. When the i-ro clock pulse is fed to the other input of the multiplier 20, a digital code is received from the output of the memory unit 19, the value of which corresponds to the amplitude of the spectral component formed in the kth time subchannel.

The law of variation of the amplitudes of the spectral components from one temporary subchannel to another is presented in the form of a table of digital codes in the memory unit 19. From the output of the multiplier 20, the signal is fed to the input of the second digital-to-analog converter 18 and to the other input of the third adder 11. The recirculating storage device, consisting of the third adder 11 and register 10, sums the samples of sinusoidal oscillations generated in all the variable subchannels within each period. In this case, the temporary subchannels are converted into one channel. Register 10 delays the signal by one time subchannel. At the end of the operation of summing the samples of sinusoidal oscillations in all time subchannels in each of the periods, the register 10 is set to zero by the signal from the output of the second counter 16 to the input of setting zero, register 10. At the trailing edge of the same signal supplied to the input of the register register 12, shown in FIG. 26, information is overwritten from the output of the third adder 11 to the register 12. The signal from the output of the register 12 is input to the first digital-to-analog converter 13, and from its output through the low-pass filter 14 to the first output of the special signal generator. The principle of signal spectrum formation at the first output of the special signal generator for the linear law of distribution of the amplitudes of the spectral components is shown in FIG. 6 a, b.

At the second output of the special signal generator there is a set of sinusoidal oscillations, and at the third output of the special signal generator there are codes of a set of sinusoidal oscillations.

Claims (2)

Claim A special signal generator comprising a clock, a first counter, a frequency determination memory, first and second adders, a first register, a controlled element NOT, a digital delay line, an algebraic adder, a second register, a third adder, a third register, a pulse shaper, a second counter , a memory block of sines, a memory block of amplitudes of spectral components, a multiplier, and the output of the clock generator is connected to the counting inputs of the first and second counters, synchronization inputs of the first and of the first registers, pulse shaper, digital delay line, the low-order output of the first counter is connected to the address inputs of the frequency determination memory block and the spectral component amplitude memory block, the output of which is connected to the first information input of the multiplier, the second information input of which is connected to the output of the sine memory block whose address input and information input of the digital delay line are connected to the output of the controlled element NOT, the information input of which is connected to the output of the algebra the adder, the first information input of which is connected to the information output of the digital delay line, the output of the pulse shaper is connected to the control input of the controlled element NOT, the control input of the digital delay line and the first control input of the algebraic adder, the second control input of which is connected to the output of the end of the digital line period ' delay, the output of the end of the period of the digital delay line is connected to the input of the initial installation of the second counter, the information input of which is connected n to the output of the bits of the conversion factor of the memory unit for determining frequencies, the outputs of the bits of 25 bits of the initial value of the argument and the changes of the initial argument of which are connected respectively to the first information inputs of the first and second adders, the output of the first register of sub-keys to the second information input of the first adder, output which is connected to the second information input of the second adder, the output of which is connected to the information input of the first register, the reset inputs of which and the second register and the recording input the third register are connected to the overflow output of the second counter, the overflow output of the algebraic adder is connected to the information input of the pulse shaper, the output of the multiplier is connected to the first information output of the generator and the first information input of the third adder, the output of which is connected to the information inputs of the second and third registers, the output the second register is connected to the second information input 15 of the third adder, the output of the third register is connected to the second information output generator, characterized in that, in order to expand the scope by independently adjusting the phase of each spectral component of the output multi-frequency signal, a phase memory unit of the spectral components and a fourth adder are introduced, and the outputs of the lower and upper bits of the first counter are connected to the corresponding bits address input of the phase memory block of spectral components, the output of which is connected to the first information input of the fourth adder, the second information input of which is is output from the first register, the output of the fourth adder is connected to the second input of the algebraic adder, gg Fig 2 FIG. 3 6) Τ “Τ> 1 * <G 1 'g · ¹ G ·' · ¹ G ¹ I 12.3U6 7 89eBW 16 l-ι I I —I I I ’· 'D' 2 4 6 δ 70 24 6 -G'- I ------ 1 I I G "1 FIG. 4 1820 I I 8U I - 1 ^ k Sip <0 f ιαϋ ~ 2 ^ LL2.6