RU2010241C1 - Device for extraction of orthogonal components of harmonic voltage of known frequency - Google Patents

Abstract

FIELD: electric measurement technology. SUBSTANCE: device for extraction of orthogonal components of harmonic voltage of known frequency has pulse generator 1, analog-to-digital converter 2, pulse counter 3, demultiplexer 4, five storing adders 5-9, five adders 15-19, divider 20, four multipliers 11-14, two registers 21,22. EFFECT: improved efficiency in extraction of orthodontia components of harmonic voltage during transition processes. 2 dwg

Description

 The invention relates to electrical engineering and can be used, in particular, in relay protection devices, when measuring the conversion of active or reactive capacities of an industrial current under conditions of an aperiodic electromagnetic transient in an electric power system.

 A device for separating the orthogonal components of harmonic voltage can be implemented by numerically integrating the products of the signal by the coefficients in the form of sinusoidal voltages based on the method described in [1].

 The disadvantage of the prototype is the relatively large error in the allocation of the orthogonal components of the harmonic voltage from its sum with an aperiodic component.

 The aim of the invention is to improve the accuracy of the selection of the orthogonal components of the voltage containing the aperiodic component.

The goal is achieved by the fact that in the device for separating the orthogonal components of the harmonic voltage of known frequency, containing two multipliers, an analog-to-digital converter (ADC), a pulse generator (GI), a delay element, two accumulating adders (integrator), two registers, a pulse counter is introduced, a demultiplexer (DMS), three accumulating adders (integrators), two multipliers, four adders, a dividing device, and the output of the pulse generator is connected to the ADC clock input, the pulse counter input, and the information DMS ode, the pulse counter output is connected to the DMS address inputs, the DMS outputs are connected to the clock inputs of the accumulating adders, the information inputs of which are connected to the ADC output, the fifth DMS output is connected to the input of the delay element, the output of which is connected to the reset input of the accumulating adders and to the outputs of the registers, the outputs of the second and fourth accumulating adders are connected to the inputs of the first adder, and the outputs of the first, second and fifth accumulating adders are connected to the inputs of the third adder, the outputs of the first and second sum mators are connected to the inputs of the division device, the output of which is connected to the inputs of the first and second multipliers, the outputs of the first and third adders are connected to the other inputs respectively, the outputs of the first and second multipliers are connected to the inputs of the fourth and fifth adders, the outputs of the third and the fourth accumulating adders, respectively; the outputs of the fourth and fifth adders are respectively connected to the inputs of the third and fourth multipliers of their input signals by a constant coefficient k = 0.5 ω T _and , where T _and are the integration time of the first, second, third, fourth and fifth accumulating adders equal to half period of industrial current, while the integration intervals are shifted relative to each other by a time value equal to a quarter of the period of industrial current, the outputs of the third and fourth multipliers are connected to other inputs of the first and second registers accordingly.

 In FIG. 1 shows a diagram of the proposed device.

 The device consists of GI1, ADC2, 3 pulse counter, DMS4, accumulating adders 5-9, delay element 10, multipliers 11-14, adders 15-19, division element 20, registers 21 interconnected.

 The device operates as follows.

U(nT₁); U_и2=

U(nT₁); U_и3=

U(nT₁);
U_и4=

U(nT₁); U_и5=

U(nT₁), где r= Т_и/Т₁ - четный; r₁= T/T₁, с выходов накапливающих сумматоров 5, 6, 7, 8, 9 поступают на входы сумматора 16, сумматора 15, сумматоров 16, 17, 18, сумматоров 15, 19, сумматоров 16, 17 соответственно. Напряжение U_и2+ U_и4 c выхода сумматора 15 поступает на входы устройства 20 деления и умножителя 11. Напряжение U_и1+2U_и3+U_и5 (здесь слагаемое 2U_и3формируется сдвигом его в сторону старшего разряда) с выхода сумматора 16 поступает на вход устройства 20 деления, а напряжение U_и3+U_и5 с выхода сумматора 17 поступает на вход умножителя 12. Напряжение (U_и2+U_и4)/(U_и1+2U_и3+U_и5) с выхода устройства 20 деления поступает на входы умножителей 11, 12, с выходов которых напряжения (U_и2+U_и4)²/(U_и1+2U_и3+U_и5) и (U_и2+U_и4)(U_и3+U_и5) / (U_и1+2U_и3+U_и5) поступают на входы сумматоров 18, 19 соответственно. С выходов сумматоров 18, 19 напряжения (U_и2+U_и4)²/(U_и1+2U_и3+U_и5)-U_и3 и U_и4-(U_и2+U_и4)(U_и3+U_и5)/(U_и1+2U_и3+U_и5) поступают на входы умножителей 13, 14, на выходах которых выделяются напряжения U_mcosφ_и1= 0,5ω Т_и[(U_и2+U_и4)²/(U_и1+2U_и3+U_и5)-U_и3] и U_msin φ_и1 = 0,5 ω T_и[U_и4-(U_и2+U_и4)х(U_и3+U_и5)/(U_и1+2U_и3+U_и5)] соответственно. Напряжения U_mcosφ_и1 и U_msinφ_и1 c выходов умножителей 13, 14 поступают на входы регистров 21, 22. На выходе элемента 10 задержки формируется импульсный сигнал, задержанный относительно последнего импульса на выходе 5 DMS4, причем значение времени задержки определяется временем протекания переходных процессов в сумматорах 15-19, умножителях 11-14, устройстве 20 деления. Выходной сигнал элемента 10 задержки записывает информацию U_mсos φ_и1, U_msin φ_и1, в регистры 21, 22 соответственно и одновременно сбрасывает значения, записанные в накапливающих сумматорах 5-9. Процесс повторяется.From the output of GI1, clock pulses are fed to the ADC2 clock input, counter input 3, and information input DMS4. A voltage is supplied to the ADC2 information input (Fig. 2), and digital values U (nT ₁ ) of this voltage with a sampling interval T ₁ allocated to the information inputs of accumulating adders 5-9 are allocated at its output. Clock pulses coming from the output of GI1 at time intervals 0-Ti, TT-T + T _and , 2T-2T + T _and , 3T-3T + T _and , 4T-4T + T _and (Fig. 2) to the information input DMS4 pass to outputs 1, 2, 3, 4, 5, respectively, depending on the address signal at the address input DMS4 coming from the output of counter 3. The signals from outputs 1, 2, 3, 4, 5 DMS4 go to the clock inputs of the accumulating adders, which allow you to record the signals coming from the output of the ADC2, in the accumulating adders 5, 6, 7, 8, 9, respectively. Signal Integral Values
U _{and 1} =

U (nT ₁ ); U _{and 2} =

U (nT ₁ ); U _u3 =

U (nT ₁ );
U _{and 4} =

U (nT ₁ ); U _{and 5} =

U (nT ₁ ), where r = T _and / T ₁ is even; r ₁ = T / T ₁ , from the outputs of accumulating adders 5, 6, 7, 8, 9 are fed to the inputs of the adder 16, adder 15, adders 16, 17, 18, adders 15, 19, adders 16, 17, respectively. The voltage U _{and 2} + U _{and 4} from the output of the adder 15 is supplied to the inputs of the division device 20 and the multiplier 11. The voltage U _{and 1} + 2U and ₃ + U _{and 5} (here the term 2U and ₃ is formed by shifting it to the higher order) from the output of the adder 16 is fed to the input of the device 20 divisions, and the voltage U and ₃ + U _{and 5} from the output of the adder 17 is fed to the input of the multiplier 12. The voltage (U _{and 2} + U _{and 4} ) / (U _{and 1} + 2U and ₃ + U _{and 5} ) from the output of the 20 division device is supplied to the inputs of the multipliers 11, 12, from the outputs of which the voltages (U _{and 2} + U _{and 4} ) ² / (U _{and 1} + 2U and ₃ + U _{and 5} ) and (U _{and 2} + U _{and 4} ) (U and ₃ + U _{and 5} ) / (U _{and 1} + 2U and ₃ + U _{and 5} ) arrive at the inputs of adders 18, 19 with responsibly. From the outputs of the adders 18, 19 voltage (U _{and 2} + U _{and 4} ) ² / (U _{and 1} + 2U and ₃ + U _{and 5)} -U and ₃ and U _{and 4} - (U _{and 2} + U _{and 4} ) (U and ₃ + U _{and 5} ) / (U _{and 1} + 2U and ₃ + U _{and 5)} are fed to the inputs of the multipliers 13, 14, at the outputs of which the voltages U _m cosφ _{and 1} = 0,5ω T _and [(U _{and 2} + U _{and 4} ) ² / (U _{and 1} + 2U and ₃ + U _{and 5} ) -U _u3 ] and U _m sin φ _u1 = 0.5 ω T _and [U _u4 - (U _u2 + U _u4 ) x (U _u3 + U _u5 ) / (U _u1 + 2U _u3 + U _u5 )] respectively . The voltages U _m cosφ _{and 1} and U _m sinφ _{and 1} from the outputs of the multipliers 13, 14 are fed to the inputs of the registers 21, 22. At the output of the delay element 10, a pulse signal is generated, delayed relative to the last pulse at the output 5 of DMS4, and the value of the delay time is determined by the transition time processes in adders 15-19, multipliers 11-14, device 20 division. The output signal of the delay element 10 records information U _m cos φ _{and 1} , U _m sin φ _{and 1} , in the registers 21, 22, respectively, and simultaneously resets the values recorded in the accumulating adders 5-9. The process is repeated.

представляющих интегралы напряжения U в виде суммы затухающей апериодической U_oe^-αt и гармонической U_msin( ωt+ φ_и1) составляющих, причем интегрирование производится за время T_и= 10 мс, а интервалы интегрирования Т_и для значений U_и1, U_и2, U_и3, U_и4, U_и5 сдвинуты относительно друг друга на интервал Т= 5 мс (фиг. 2). Решение системы уравнений (1) относительно ортогональных составляющих имеет вид

Очевидно, что выражения (2), являющиеся корнями системы уравнений (1), имеют мес-то практически при всех значениях параметров U_o, α , U_m, φ_и1.The action of the proposed device is based on solving a system of equations

representing the voltage integrals U in the form of the sum of the damped aperiodic U _o e ^-αt and harmonic U _m sin (ωt + φ _и1 ) components, moreover, integration is carried out in a time T _and = 10 ms, and integration intervals T are _also for values of U _{and 1} , U _{and 2} , U and ₃ , U _{and 4} , U _{and 5 are} shifted relative to each other by the interval T = 5 ms (Fig. 2). The solution of the system of equations (1) with respect to the orthogonal components has the form

Obviously, expressions (2), which are the roots of the system of equations (1), occur at almost all values of the parameters U _o , α, U _m , φ _{and 1} .

Reliability of relations (2) is confirmed by calculations on a MK -61 programmable calculator. So, for example, according to the prototype at U _m1 = U _o = 1 V, φ _and 1 = 1 rad. , T ₁ = 1 ms, α = 200 s ^-1 reduced error of measurement of the orthogonal components U _m sin φ _u1 and U _m cos φ _u1 is 32 and 51%, and for φ _u1 = 3 rad. , T ₁ = 1 ms, α = 50 s ^-1 these errors are 15 and 100%, respectively. When using formulas (2), there is no calculation error. Moreover, the calculations according to the proposed formulas (1), (2) were performed in the presence of the second harmonic U _m2 sin (2ωt + φ _{and 2} ) at voltage u (Fig. 2), the integral value of which is zero at T _and = 10 ms. (56) 1. Fedoseev A.M. Relay protection of electric power systems. Relay protection of networks: Textbook. manual for universities. - M.: Energoatomizdat, 1984, p. 520, p. 266-268.

Claims (1)

 Highlighter orthogonal component harmonic voltage known frequency of its amount with apepiodicheskoy component sodepzhat two multiplier, analog-DIGITAL Transmitter, paralleling points pulses the delay the element, two collecting summatopa two registers, ppichem pulse output of generators connected to sinhpovhodom analog-DIGITAL Transmitter yield which is connected to the information input of the first accumulating adder, the output of the delay element is connected to the inputs of recording registers, the outputs of the first and second registers connected to the corresponding outputs of the device, characterized in that it includes a pulse counter, a demultiplexer, three accumulators, two multipliers, five adders, a division element, and the information input of the analog-digital converter is connected to the input of the device demultiplexer input and pulse counter input, the output of which is connected to the address inputs of the demultiplexer, from the first to fifth outputs of the demultiplexer are connected to the clock inputs of the corresponding of accumulating sums, information inputs from the second to fifth accumulating sums are connected to the output of an analog-to-digital converter, the fifth output of the demultiplexer is connected to the input of the delay element, the output of which is connected to the inputs of the reset accumulating sums of the total the outputs of the first, third and fifth accumulating adders are connected to the inputs of the second adder, the outputs of the third and fifth accumulating adders are connected to the inputs of the third ummatora, the outputs of the first and second totalizers are connected to the inputs of the division element, the output of which is connected to the first inputs of the first and second multipliers, the second inputs of which are connected to the outputs of the first and third sums of the fourth, fourth and fourth the second inputs of which are connected to the outputs of the third and fourth accumulating adders, respectively, the outputs of the fourth and fifth adders are connected to the inputs of the third and fourth multipliers, respectively but outputs eccentricity infopmatsionnymi coupled to inputs of first and second type of registers, respectively.

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