SU830631A1 - Device for control of self-sustained inverter - Google Patents

Description

one

The invention relates to a conversion technique and can be used in converters with pulse-width and .pulse modulation.

Control devices for stand-alone, pulse-width-modulated inverters are known, in which the output voltage is generated using analog signals 1.

However, the data is simple, the devices require hard parameters of analog signals, which is difficult to implement.

Also known are digital controls for autonomous inverters with WID 2.

The disadvantage of these devices is the constant voltage value during the adjustment process.

The closest in technical essence to the present invention is a control device for an autonomous inverter with WID, containing a control unit connected by an output to the input of a ring counter, clock generator, counter of the period of the carrier frequency connected to the clock unit and the ring counter, latitude -pulse drivers by the number of phases, connect

Connected to the respective outputs of the clock unit and the carrier frequency period counter, the driver units for controlling the inverter valves. An analog-to-digital driver consists of a master oscillator of the output voltage of the inverter, a key of a Voro device, and a meter connected in series. The pulse width pulse pulse shaper consists of an intermediate register and a comparison circuit of phase counter codes and an intermediate register connected in series. Control device

5, the autonomous inverter provides independent control of the output frequency and voltage of the inverter 3.

However, this device reduces

0, the actual value of the first harmonic of the output voltage, moreover, it does not provide high accuracy of regulation, since it requires simultaneous control of the output frequencies of the generators in the output frequency control channel and in the voltage control channel.

The purpose of the invention is to increase the efficiency and accuracy of control.

0 converter.

The goal is achieved by additionally inserting into the known device an operation switch of the inverter groups, two adjustable frequency dividers, modulators for the number of phases, each of which are connected by outputs to the inputs of the corresponding pulse-width driver, and the inputs are connected to the corresponding outputs of the control unit ,

1st and 2nd adjustable frequency dividers, a clock unit and a ring counter, the outputs of which are connected via the switch of the inverter groups to the outputs of the pulse-width drivers connected to the corresponding: driver units, with the inputs of the 1st and 2nd frequency dividers connected to the outputs of the clock generator and the control unit, and the output of the 1st divider to the inputs of the period counter and the clock unit.

The modulator contains an encoder, a counter, a reverse unit, a reversible counter and a switch, the outputs of which are connected to the corresponding inputs of the encoder, a counter and a reverse unit connected to the outputs of the summing and subtracting inputs of the reverse counter, connected to the inputs of the switch, and the encoder's inputs are connected with the outputs of the control unit and the ring counter, one of the inputs to the VU1utator, together with the input of the unit, the reverse is connected to the output of the 1st adjustable frequency divider, and the other inputs to the outputs 2-gO divides L frequency Timing circuit and ring counter, adjusting input of down counter connected to the timing unit, and outputs - to the intermediate register the pulse width shaper.

FIG. 1 is a diagram of a device for controlling an autonomous inverter; in fig. 2 - inverter circuit; in fig. 3, 4 and 5 are voltage diagrams.

The device contains a control unit 1, a generator of 2 clock pulses, adjustable dividers of 3 and 4 frequencies, a period counter 5; carrier frequency, clock unit 6, ring counter 7, switch 8 of the type of operation of inverter groups, modulators 9-11 according to the number of phases of the inverter, pulse-width drivers 12-14 according to the number of phases of the inverter, blocks 15-17 of drivers for controlling the valves 18 an inverter connected to the motor 19. The modulator comprises an encoder 20, a counter 21, a reversible counter 22, a switch 23 and a reversal block 24. Shaper 12 contains master 25, block 26 of code comparison block 27 of the reverse, trigger 28.

The device works as follows.

Using the control unit 1, the frequency and voltage of the inverter are controlled by setting the frequency division factors of the 2 clock pulses and the initial conditions of the voltage characteristic from the frequency worked by the adjustable frequency dividers 3 and 4 and the modulators. The carrier frequency period counter 5 serves to create an interval of quantized values of the phase of the switching moment of the inverter power valves, the duration of which is equal to the carrier frequency period. Using the ring counter 7, the ratio between the carrier and output frequencies of the inverter is set and the operation of the modulators is controlled in accordance with a shift of 120 J PH output modulated voltages on the motor fanza. The switch 8 of the operation of the inverter groups serves to change the order of switching of the inverter valves in accordance with the change in the sign of the derivatives of the curves of modulated voltages. Modulators 9-11 serve to create reference time intervals and further convert these intervals into a code proportional to the average value of the inverter voltage over carrier frequency periods, in accordance with the inverter output frequency, load, and sinusoidal voltage modulation. Pulse Width Drivers are used to convert the modulator code into a pulse width signal, with which the gates entering the inverter phase are controlled. With the help of blocks 15–17 formers, the control signals of the power and auxiliary valves of the inverter are formed and they are galvanically isolated. When the inverter is operated with a pulse-width modulation (Fig. 2), the thyristors of the anode group VI-V3 and the cathode group V2-V6 switch repeatedly during the period of the output frequency of the inverter. The switching frequency of the thyristors is determined by the carrier frequency, and the average value of the voltage by the ratio of the durations of switching on the thyristors of the anode and cathode groups over the period of the carrier frequency. Any mismatch between the turn-on times of the thyristors entering the inverter phase from the middle of the carrier frequency period results in a positive or negative voltage at the output. FIG. Figure 3 shows the control pulses of the anode group of the thyristor inverter with sinusoidal modulation and the corresponding voltage diagrams of Ud, U, and and, on the phases of the asynchronous motor 19 when the motor windings are connected into a star. The cathode group control pulses supplement the thyristor control pulses of the anode group up to the carrier frequency period. When adjusting the rotational speed of an asynchronous motor, the voltage at the output of the inverter is regulated in the frequency and torque functions of the motor shaft. FIG. Figure 4 shows the dependence of the voltage on the frequency, which makes it possible to realize a law close to the control law with compensation for the voltage drop on the motor stature on the load current. The slope of the curves and their initial conditions are determined by the value with respect to (Load moment - {еТ, where M is the torque due to the load; Mj is the nominal torque of the motor. The inverter thyristor control pulses in accordance with Fig. 3 are generated by the digital control device (Fig. 1) operating as follows: The output frequency of the inverter is set by successively dividing the pulses of the generator 2 (Fig. 5a) with a frequency divider 3, a period counter 5, a ring counter 7. Herewith, using a carrier period period counter 5 the reference interval (Fig. 5d) of the quantized values of the phase of the switching moment of the thyristors included in the phases of the inverter is created, and using an annular counter 7, the ratio of the inter-carrier and output frequencies of the inverter is set. Formation of a code proportional to the phase of the switching moment of the anode thyristor groups on the thyristor of the cathode group or vice versa for the inverter inverter, is carried out as follows: At the moment of the transition of the counter 5 through zero, a pulse is produced at the output of the clocking circuit. 5d), which goes to the switch 23 modulators. At the same time, a gate pulse is generated at the switch output to input an additional number into the counter 21 by the encoder 20, and the first series of pulses from the output of divider 3 begins to arrive at the input of the counter 21 (Fig. 56). When counter 21 overflows with the help of switch 23, a second gating pulse is generated and another installation is entered into the counter, and second-series pulses from the output of divider 4 begin to enter its input (Fig. 5c). The secondary overflow of the counter produces a signal that prevents the passage of pulses to the input of the counter 21. During the period of testing by the counter 21 of two series of pulses, one of the inputs of the reversible counter 22 through the block 24 of the reverse receives pulses of the divider 3. At the beginning of each period the carrier ch The clock code fixed by the reversible counter is transmitted to the intermediate register 25 of the pulse-width converter and at the same time the counter is reset; initial state. At the same time, the number N / 2 is fixed on account 21, and on the intermediate register - N / 2 + nd, Ы, I where / N is the number of possible states of the period counter; LK - the number of pulses that torsioned to the input of the reversible 6 counter during the time when the counter is working 21 two series of pulses. The sign of the AN number and its value is determined by the number of the carrier frequency period and the corresponding state of the period of the output of the Krz counter 7. In accordance with the indicated states, the switch 22 sets the direction of pulse passing through the 24-reverse unit to the summing or subtracting inputs of the counter 22 and No settings entered by the encoder 20. When transferring through the modulated voltage curve, such as phase L of the motor, the signal from the output of the ring counter 7 imposes a prohibition on the start-up cycle of the switch 22, respectively modulator. At the same time, the settings on the counter 21 are not entered and the pulses do not pass through the block 24. The operation of the modulators 9-11 is shifted by 120, which is achieved by appropriately connecting the outputs of the ring counter to the encoders of the modulators. The conversion of the code recorded by the register 25 into a pulse-width signal occurs as follows. In accordance with the law of switching of the inverter valves (Fig. 3), the signals from the ring counter 7 are selected by means of the group operation switch 8 to select the operating thyristor of the inverter phase at the beginning of the carrier frequency period. The signals from the output of the switch 8 determine the channel of the pulse passing. The beginning of the period through the block of the reverse 27 of the pulse-width modulator to the input three. 28. Thus, the state of the trigger 28 at the beginning of the carrier frequency period is determined. The secondary flip-flop of trigger 28 occurs when the signal Equals at the output of the comparator block 16, which performs a one-to-one comparison of the codes of the counter 5 and the register 25. The equal signal (Fig. 5, e) appears at the moment of equality of the current code of the counter 5 period and code fixed by intermediate register 25. A change in the order of operation of the inverter groups occurs each time that the second half of the negative or positive voltage half-period for the motor phases A, B and C is formed (Fig. 3). In this case, the impulse. The beginning of the period confirms the previous state of the signals at the outputs of the trigger 28 (Figs. 5e and 3h). Fig. 5c shows the state of one of the trigger outputs, corresponding to the thyristor control pulses 2 (Fig. 3) in the second and third periods of the carrier frequency, using a signal taken from the second trigger arm, the thyristor control signals 2 are generated. the outputs of the trigger 28 (Fig. 5h) of the pulse-width formers are transferred to the corresponding block of the formers 15-17, with the help of which the power O and auxiliary thyristors are controlled, which enter the inverter phase.

The voltage is controlled as a function of the moment of load on the motor shaft by means of block 1. In this case, according to the control signals of block 1, the division factor of the clock pulses of the adjustable divider 4 is changed and the channels are tuned, the settings entered by the encoders 20 are adjusted to work out the first series of pulses proportional to This is equivalent to a change in the reference time intervals, ut, formed by the modulators. In the process of controlling the output frequency of the inverter, the depth modulation factor of the voltage is limited. In order to avoid disruptions of the inverter operation at a nominal extraction rate, the counter counter code 22 is analyzed. If the code value corresponds to the r-dimly possible recovery time of the control properties of the thyristors entering the inverter phase, the switch on the passage of pulses 23 is imposed the input of the counter 22 through the block 24 of the reverse. In order to: ensure contactless reversing of the induction motor, the order of operation of the phases of the inverter is changed. This is achieved by changing the control signal from block 1, which is changing the counting direction of the ring counter 7. The state of the outputs of the counter 7, which determines the order of operation of the modulators, corresponds to the reverse phase rotation.

The introduction of new elements makes it possible to expand the field of application of the proposed device, because, regardless of the type of load, a single-phase or three-phase voltage controlled by the pulse-width modulation method at the carrier frequency retains its qualitative character. In addition, in comparison with the known, almost any law of optimal control of an asynchronous motor can be implemented. The accuracy of testing the specified values increases.

Claims (3)

1. A device for controlling an autonomous inverter containing a control unit connected by an output to the input of a ring counter, a clock generator, a carrier period counter 4acTpTHj. connected to the clock unit and ring counter pulse-width drivers by the number of phases connected to the corresponding outputs of the clock unit and a carrier period counter, driver units for controlling inverter valves, characterized in that, in order to increase efficiency and control accuracy, the device is equipped with a switch of operation of inverter groups, two adjustable frequency dividers modulators for the number of phases, each of which is connected by outputs with the inputs of the corresponding pulse-width driver, and the inputs are connected to the corresponding outputs of the control unit, the 1st and 2nd adjustable frequency dividers, the clock unit and the ring center The outputs of which through the switch of the inverter groups are connected to the inputs of pulse-width drivers connected to the corresponding blocks of drivers, and the inputs of the 1st and 2nd frequency dividers are connected to the outputs of the clock generator and the control unit, and the output of the 1st divider - to the entrances. period counter and clock unit. 2. The device according to claim 1, characterized in that the modulator comprises an encoder, a counter, a reverse unit, a reversible counter and a switch, the outputs of which are connected to the corresponding inputs of the encoder, the counter and the reverse unit connected to the outputs of the summing and subtracting inputs of the reverse counter, connected to the inputs of the switch, and the encoder inputs are connected to the outputs of the control unit and the ring counter, one of the switch inputs, together with the input of the reverser unit, is connected to the output of the 1st adjustable divider frequencies, and other inputs to the outputs of the 2-g frequency divider, clocking circuit and ring counter, the installation input of the reversible counter is connected to the clocking unit, and the outputs - to the intermediate register of the pulse-width imager. Sources of information taken into account in the examination 1. Sandler A.S. Gustsky Yu.M. Thyristor inverters with pulse-width modulation for controlling asynchronous motors. M., Energie, 1968. 2. Authors certificate of the USSR 251669, cl. H 02 R 13/18, 1970. 3.Patent UK No. 1267939, 5 cl. H 2 F, H 2, 1964. INP HI They n. ex. Yj 11np cpr V5 BUT