SU1267375A1 - Device for controlling velocity of electric motor - Google Patents

Abstract

The invention relates to automatic control systems and can be used, for example, in high-precision frequency controllers for the rotation of electric drives of paper machines, lines for the production of polymeric materials and other production mechanisms. The purpose of the invention is the expansion of functional classes 05 1 CO SP

Description

capabilities and increase device performance. The scan of the counter code 37 into a pulse-number sequence, characterizing the phase increments at fixed time intervals, is carried out using a converter - a code into pulse sequence 3 and a reference counter 11, to the input of which the generator pulses 10 are received. Using intermediate frequency divider 4, the agreement between the rate of change of the phase of the supply voltage of the sensor of the angle of rotation of the motor shaft 27 and the frequency at the output of the code converter into the pulse sequence 3. C is stuck Signals from the speed master 1 signals, which characterize the direction of motion, the pulses from the intermediate frequency divider 4 are fed through the reverse block 5 to the summing or subtracting input of counter 6, the phase increment pulses are generated at one of the outputs of the phase increment calculator 32. The component of the control law is proportional, A DAC 8 is formed corresponding to the speed reference of the engine. In this case, depending on the direction of rotation of the engine, according to the signals from setpoint 1, using the switch 9, Dietz selection voltage supplied to the input of the speed control system circuit. The equivalent speed controller includes an angle error shaping channel, as well as analog speed controller 20, and is a combined proportional-integral controller. The proportional component of the regulation law is calculated from the deviation of the motor speed reference and feedback signal from speed sensor 23 in analog form. The digital component of the regulation law is formed by a phase-to-code converter 25 and corresponds to an integral of the difference between the reference speed and feedback. The digital signal from the converter 25 is converted by the DAC 24 into a voltage that is summed with the proportional component and is fed through the amplifier 21 to the motor, which is used to control and stabilize the speed of the control object in disturbance and control modes. 5 il.

The invention relates to automatic control systems and can be used, for example, in high-precision speed controllers for electric drives of paper-making machines, lines for the production of polymeric materials and other production mechanisms.

The purpose of the invention is to expand the functionality and increase the speed of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 illustrates a channel for converting rectangular pulses into sinusoidal stresses; Fig. 3 is a square pulse shaper; Fig. 4 illustrates a read pulse shaper; on Fig.5 decryptor and multiplexer.

A device for controlling the speed of an electric motor (Fig. 1) contains a serially connected speed master 1, a digital intensity master 2, a code converter in pulse sequence 3, an intermediate frequency divider 4, a reverse unit 5 and a reversible counter 6, a clock unit 7, a series-connected digital-analog converter 8 and the switch of the sign 9, connected in series to the clock pulse generator 10, the reference counter 11, the two most significant bits of which are connected to the inputs of the decoder 12, the block comparison of codes 13, connected by inputs with the lower bits of counters 6 and 7, and output with gate inputs of multiplexers 14, .15, 16 and 17, informational inputs of each of which are shifted by one relative to the previous multiplexer are connected to the outputs of the decoder 12 , and control inputs to the two most significant bits of the reversible counter 6, two triggers 18 and 19, connected by inputs to the outputs of multiplexers 14, 15, 1.6 and 17, respectively, connected in series analog speed controller 20, power amplifier 21 and electric motor 22, the output of the speed sensor 23 is connected to the input of the speed regulator 20 connected by a second input to the output of the toggle switch 9, and the third through a digital-to-analog converter (D / A converter) 24, a phase-code converter 25 and a shaper of the angle pulses 26 the motor shaft 27, the outputs of which are connected via a converter 28 rectangular pulses into sinusoidal voltages with the outputs of flip-flops 18 and 19, the sequentially connected element I 29, a reversible counter 30 a two-channel divider frequency 31, phase increment calculator 32, phase-to-code converter 33. In turn, digital intensity master 2 contains serially connected pulse generator 34, synchronization unit 35, reverse unit 36, reversible counter 37, code comparison unit 38 whose outputs are connected to the inputs of the reverse unit 36, and the second inputs - to the outputs of the unit speed 1, and the second input of the synchronization unit 35 is connected to the output of the generator 10 clock pulses. The code converter in pulse sequence 3 consists of a block 39 of comparison of codes, triggers 40 and 41, element 42, two outputs of which are connected to the outputs of triggers 40 and 41, one of the inputs of trigger 40. Jointly with the input of trigger 41 is connected to the first the output of the clock unit 7. The second output of the clock unit 7 is connected to the second input of the trigger 41, the second input of the trigger 40 is connected to the output of the code comparison unit 39, the second input of which is jointly with the third input of the And element 42 and the first input of the clock unit 7 is connected to Gene Generation rarator 10 clock pulses, and the third input. In conjunction with the second inputs of the timing unit 7, to the outputs of the reference C1 detector I 1, the first inputs of the code comparison unit 39 are connected to the outputs of the intensity counter 37 of the inverter, a. the output of the element 42 and to the input of the frequency divider 4, the converter phase-code 25 contains a register 43 and a driver shchitschani 44, the output of which is connected to the clock input of the register 43 connected by information inputs with the outputs of the reference counter 11, and the outputs with the inputs DAC 24. The first, second and third inputs of the imaging unit 44 are connected respectively to the outputs of the imaging unit 26, the clock pulse generator 10 and the element AND 29. The second phase-code converter 33 consists of a register 45 and the imaging unit 46 One other input to the output of the imager 26, and the other to the intermediate discharge of the reference counter 11, the remaining outputs of the counter, beginning with the next discharge relative to the intermediate one, are connected to the information inputs of the register 45 and the phase increment calculator 32, the second inputs of which are connected to the outputs of the register 45. The clock input of the register 45 together with the third input of the phase increment calculator 32 is connected to the first output of the read pulse generator 46, the second output of which is connected to the fourth input b Phase 32 phase increment calculation. Each of the two channels (FIG. 2) of the converter 28 of rectangular pulses contains resistors 47 - 59 ,. potentiometer 60, capacitors 61-69, opamp 70, 71 and 72,. transformer 73. Shaper 26 (fig.Z) consists of resistors 74-83, capacitors 84-89, operational amplifiers 90 and 91, transistor 92 and diode 93. Shaper 44 (fig. 4) contains an HE 94 inverter, two triggers 95 and 96, element AND 97, Decoder I2 consists of two HE 98, 99 inverters and four AND 100-103 elements, and each of the multiplexers contains two HE 104, 105 inverters, four AND elements 106-109 and an OR element 110 (FIG. 5 ) 1 The principle of operation of the measuring part of the device (FIG. 1) is based on the power supply of the angle-of-turn sensor of the sine-cosine transforming type the torus is a sinusoidal voltage V, V8in (of + cp) 5 Vco8 (wfitf), (1) the output voltage of the sensor can be represented as follows V, "(tOf ± (f) sinCt6) ± ± V) fi (; F) cos (+0) | "- mVsin (of ± (| ie), where V is the voltage amplitude; Cf is the phase of the supply voltage, the change of which in time characterizes the required law of motion; the angle of rotation of the sensor; the transformation ratio; angular velocity; time. From the last expressions that the angle error information () is needed is contained in the output voltage V phase, with respect to the reference voltage Vsinwfo. This allows reading the information on the angular mismatch in digital form at the current interval of the reference counter without intermediate transitions. Lagging and increasing the speed of the regulating system. The speed of change of the voltage phase of the sensor of the angle of rotation 27 is formed as follows. From the output of the speed setting I. The code of the reference goes to the digital intensity setting 2, which ensures constant acceleration. during periods of acceleration and deceleration of the engine, Depending on the codes of the speed control unit 1 and the reversing counter 37, the outputs of the comparison block of codes 38 produce more or less signals that are allowed The passage of the pulses of the generator 34 through the reverse 36 block to the summing or subtracting inputs of the reversible counter 37. This causes an increase. or a decrease in the code of the reversible counter 37 until it becomes equal to the number at the output of the speed setpoint 1, For the purpose of synchronization the operation of the device blocks the generator pulses 34 are synchronized with the clock pulses of the generator 10 clock pulses in the synchronization unit 35, wherein along the leading edge of the generator pulses 34, whose frequency corresponds to the required acceleration, forms ruyuts pulses of the same frequency and duration ravyoy timing pulses at the initial moment of time corresponding to the power feeding apparatus sbrasshaets down counter 37 to the zero state. This eliminates the formation of acceleration from intermediate speed stages. Further, using the reversible counter 37, the current number at the output of the speed controller 1 is continuously monitored. The counter 37 code develops into a number-pulse sequence characterizing the phase increments at fixed time intervals. using the converter code in the pulse sequence 3 and the reference counter 11, the input of which receives the generator pulses 10, At the moment of transition of the counter 11 through a zero at the output of the clock unit 7, with the help of which the state of the counter code is deciphered, a start of the cycle signal is generated, the trigger 41 triggers. This leads to the appearance of a signal allowing the generator 10 pulses to pass through the And 42 element, the prohibition of the passage of these pulses is generated at the moment of equality of the codes of the counters 11 and 37, At the same time, at the output 6hoKa 39 of the code comparison, performing: bitwise comparison of the codes, the signal Equals, the tilting trigger 40, At the inversion output of the triggers Era 40 appears a zero signal level, which prohibits the passage of pulses through element 42. To eliminate spurious pulses at the output of element 42, the signals produced by blocks 7 and 39 are synchronized by generator pulses 10. Thus, the formation of a time interval proportional to the counter code 37 and the corresponding burst at the output of the element 42. The flip-flops 40 and 41 return to their initial position according to the signal. The cycle end of the clock unit 7, which is formed at the maximum value of the code using the intermediate frequency divider 4, a matching is made between the rate of change of the phase of the supply voltage of the angle sensor of the motor shaft 27 (angular speed of the engine) and the output frequency of the code converter in the pulse sequence 3. At the same time, the non-uniformity of the pulse is smoothed . Depending on the signals of the speed reference 1, which characterize the direction of movement, the pulses from the intermediate frequency divider 4 are fed through the reverse block 5 to the summing or subtracting inputs of the counter 6. For powering the sensor 27, rectangular pulses are formed, the phase shift of which is relative to the beginning of the reference counter period 11 is equal to counter code 6. Phase shifts 11/2 during the formation of sinusoidal and cosine strain are provided by allocating four intervals on the period of operation of the reference counter using decoder 12 (Fig. 3) For this, the signals from the two most significant bits of reference counter II are inverted by HE elements 98, 99 and their combined i combination is fed to the inputs of elements And i00-103. The signal 1 at the output from the elements AND of the decoder determines the current interval corresponding to the code of the reference counter number J 1. The position of the leading edge of the pulses corresponding to the transition of the positive half-wave of the sinusoidal voltage formed through zero is determined by the code of the reversible counter 6. At the same time the two most significant bits of counter 6 determine the initial sweep interval of reference counter II, and the lower ones determine the position of the phase of the inner interval. The leading edge of the pulse is formed with a shift by T or two intervals in comparison with the initial one. The fronts of the cosine voltage pulses are formed with a shift by one relative to the sinusoidal voltage, and the moments of their formation are determined similarly. Accordingly, the channel for passing signals from the decoder 12 through multiplexers is determined by the state of the two most significant bits of the counter 6. According to the combination of signals from counter 6 and the inverters HE 104, 105, one of four AND 106-109 elements is selected, which carry out the decoder signals 12 to the output of multiplexers through the element OR 110. If the code of the two most significant bits of the counter is 6 (00), then the signals can pass only through the element AND 106 of the multiplexers. In this case, the pulses at the output of the multiplexer 14 (Fig. 5) are formed at the 1st interval, and at the output of the multiplexer 16 - at the 3rd sweep interval. The moment of formation of pulses within the interval is determined by the gate signal from the code block 13 when the lower bits of counters 6 and 1I are equal. These pulses from the outputs of the multiplexers are supplied to the flip-flops 18 and 19 of the R-S type, which are used to form rectangular voltages shifted relative to each other by T / 2. The outputs of the decoder 12 is connected to the inputs of each subsequent multiplexer with a shift by one relative to the inputs of the previous multiplexer. This ensures a constant order of alternation of output pulses of multiplexers with respect to the initial interval. The rectangular pulses from the shoulders of the flip-flops 18 and 19 are fed to the transducer of the rectangular pulses 28, where the first harmonic of each of the signals is extracted and the power of the sinusoidal and cosine-voltage voltages described by equation (l) is amplified. Converter 28 contains two similar channels (FIG. 2), or the output of each of which includes a lower clock filter, implemented on the basis of operational amplifier 70, resistors 47, 48, 49, and capacitors bb, 62, .63. The first harmonics of the first harmonics: and rectangular pulses from the trigger output are preliminarily separated. Further formation of a sinusoidal voltage and its amplification by power is carried out by an active filter assembled on operational amplifiers 71 and 72, at the input of which a high-pass filter is turned on resistor 50, capacitor 64, and in a feedback circuit a load filter (on resistors 56 -58 and capacitors 66-68), the amplitude and phase transducer channels are adjusted by potentiometer 60 and fitting the parameters of a capacitor 64, a resistor 50, a capacitor 65 For galvanic isolation and matching the output of the power amplifier 72 with the supply voltage of the sensor. A transformer 73 is used. Excluding short circuits in case of generation failure and limiting the currents in the primary winding of the transformer is carried out by a resistor 59 and a capacitor 69. The voltage from the secondary windings of the transformers of the converter 28 is fed to the UGA sensor. rotation 27 (sine-cosine rotary transformer or revolver), through which position feedback is realized. On the output winding of the sensor 27, a voltage is generated in accordance with the expression (2). This voltage is then amplified and formed into rectangular pulses by the former 26 (Fig. 3). The shaper immunity is ensured by the inclusion of a bandpass filter on resistors 74-79 and capacitors 84-88 through the two inputs of the operational amplifier 90. The signal from its output through the high-pass filter on the capacitor resistor 80 is fed to the input of the operational amplifier 91, which operates in relay mode. Matching the output voltages of the amplifier 9 with the level of the control signals of the osc: inverter, assembled on the transistor 92f diode 93 and resistors 82 83. To ensure symmetry, the characteristics of the output voltage of the DAC 24 from the phase mismatch of the output voltage of the DAC 24 are shifted by half the maximum value, and the time of reading the information is shifted by an angle of 17. With the help of the read pulse generator 44 (FIG. 4) of the converter 25, a pulse is generated on the trailing edge of the voltage from the driver 26, respectively There is a transition of the negative half-wave of the output voltage of the sensor 27 through zero. In order to synchronize the moment of reading information to the operation of the reference counter 11, the signal processing in the generator 44 is carried out using the clock pulses of the generator 10. For this, using the trigger 95, the preliminary synchronization and repetition of the pulses driver 26. The state of flip-flop 95 is recorded on flip-flop-96, and at the moment of its tilting on output of the AND 97 element, an impulse to form a hell is formed, through which Write on the converter-phase register 43 of the current code of the reference counter 11. As a result, at each read interval of register 43, the value of the phase of the output voltage of the sensor 27 (angle error due to shift) is recorded, expressed in binary code, which is received through CDL 24 In the electric drive, in order to increase the permissible accelerations during the periods of start-up and braking, a blocking device against overturning of the drive was introduced into the device, which is introduced when the misalignment is exceeded. nor in the phase t T (1-1 / 2), where n is the number of bits of the reference counter 1I; (the number of its intermediate bit, the output signals from which are used as clocks in the channel constraints. The signals from the i-th bit of the counter are fed to the input of the read pulse generator 46 of the phase-code converter 33, which performs the selection of single pulses on the front and rear edges signals from the generator 26 and their reference to the operation of the counter 11, in this case, the signals c. + -and AND are used as information signals sent to the register 45 of the phase-code converter 33 and the block for calculating the phase 32 devices. ASP rows reference counter. The information about the phase mismatch on the register 45 is read on the leading edge of the signals from the imaging unit 26, and transferred to its storage in the phase increment calculation unit 32. on the trailing edge. In block 32, the phase code stored in the previous interval is compared with the current code of the reference counter 11 and the time code is filled.

the interval between pulses generated at the moment of equality of the specified codes and on the leading edge of the signals from the imaging unit 26, pulses from the "-th digit of the reference counter 11. Thus, the phase increments of the output voltage of the angle sensor in the pulse code are calculated, and their sign is taken into account in the order of the JL consistency of the indicated pulses, according to which the increment pulses are generated at one of the outputs of the phase increment calculator 32,

- These increments are fed to a two-channel frequency divider 31, made on the basis of a reversible counter. If divider 31 is in the initial state, then when () pulses of one character arrive at its output, an overflow pulse is formed. According to this impulse, the divider 31 returns to the initial position corresponding to the number N. At the same time, the counter code 30 changes from its zero value and the element 29 produces a prohibition signal for the formation of information read pulses by the element 97 of the converter 44 phase-code converter 25. With the elimination of the phase error exceeding its permissible value, this prohibition is lifted. A plot of the characteristics of the output voltage of the DAC 24 against the angle error is formed.

The proportional component of the law of regulation corresponding to the reference for the engine rotational speed is formed by the DAC 8. At this, depending on the direction of rotation of the engine, signals from the speed setting 1 select the voltage input to the input of the speed limit of the control system. The equivalent speed controller includes an angle error shaping channel, as well as analog speed controller 20 and is a combined proportional-integral controller. The proportional component of the regulation law is calculated from the deviation of the motor speed reference and the feedback signal from speed sensor 23 in analog form. Digital component

the law of regulation is formed by a phase-code converter 25 and corresponds to the integral of the difference between the speeds of the task and the feedback. The digital signal from converter 25 is converted by DCA 24 into a voltage that is added to the proportional component and fed through amplifier 21 to the engine, through which control and stabilization of the speed of movement of the object of control in the modes of action of disturbances on the load and control is obtained.

Thus, changing the principle of operation of the channel for forming an angle error and introducing new elements into the proposed device improves the speed of the control system, since the information on the angular mismatch is read and converted in one cycle of the reference counter. This is also achieved by setting the signal proportional to speed using high-speed digital-to-analog converters. In addition, in comparison with the prototype, its functionality is expanded. The proposed device can be used both to regulate the speed of a single engine and a group of electric motors connected by a single technological process. In the latter case, the speeds of the electric motors can be set independently of one another using the output signals of the clock generator as a base frequency, or with respect to the pulses from the output of the code converter to the pulse drive master drive.

Claims (1)

Invention Formula A device for controlling the speed of an electric motor, comprising a speed master, a code comparison unit, a series-connected clock pulse generator, a reference U-bit counter connected by outputs, with the exception of two high-order bits, to the first inputs of the code comparison block, serially connected rectangular pulse converter in sinusoidal voltage, the angle of rotation of the shaft 131 of the electric motor, the driver of the rectangular impulses, the first converter phase-code, the unit c. phase channel, two-channel frequency divider and the first reversible counter, serially connected speed controller, power amplifier and electric motor covered by negative feedback through the speed sensor, the second inputs of the first phase-code converter and the phase increment calculator are connected to the corresponding (n-1) th most senior bits of the reference counter, the third and fourth inputs of the unit for calculating the phase phase are connected respectively to the second and third outputs of the first converter, phascode, ex. Ensuring that, in order to expand the functionality and speed up the device, element I, two triggers, block clocks, a decoder, four multiplexers, a serially integrated digital intensity sensor, a code converter into a pulse sequence, an intermediate frequency divider, a reverse unit and a second reversible counter, connected in series by a nepBrfi digital-to-analog converter and a sign switch, connected by an output to the second input of the speed regulator and the second input together with the second input of the reverser block to the first sign output of the speed master, the second phase-code converter and the second digital-to-analog converter connected by output to the third input of the speed regulator are connected, the first and second control inputs of multiplexers connected to the (n-1) th and n th senior bits of the second reversible counter,. P-2, the lower bits of which are connected to the corresponding second 751 inputs of the code comparison unit, connected by the output to the strobe the inputs of the multiplexers, the information inputs of each of which are shifted by one relative to the previous multiplexer are connected to the first, second, third and fourth outputs of the decoder, the inputs of which are connected to two senior bits of the reference counter, the output of the first and third, second and fourth multiplexers are connected respectively to the inputs of the first and second Triggers, the outputs of which are connected to the inputs of the converter of rectangular pulses into sinusoidal voltages, the output of the clock generator and The pulses are connected to the first input of the clock unit, to the second inputs of the digital setpoint generator HHfeHCHSHOCTH, the code converter to the ampulse sequence and the second converter phase-code connected by the third inputs together with the third inputs of the code converter to the pulse sequence and the second inputs of the clock unit to the corresponding n bits of the code converter the counter, two outputs of the clock unit are connected to the fourth and fifth inputs of the code converter in the pulse sequence, the inputs of the first digits An analog converter is connected to the corresponding outputs of a digital intensity adjuster, the first n inputs of which are connected to the corresponding second control outputs of the speed limiter, the first input of the second phase-code converter is connected to the output of the square pulse former, and the output of the And element is connected to the fourth fourth input of the second converter the phase is the code, and the inputs are connected to the outputs of the first reversible counter. FIG. 2 7tf f 77 NGN 4 .. J -75P75 OUTLINE needles u 3 From OSI Outputs FIG. five n-f