SU815939A2 - Device for determining information authenticity - Google Patents

Description

(54) DEVICE FOR DETERMINATION OF RELIABILITY

INFORMATION

The device for determining the reliability of information contains the first 1 and second 2 shift registers, the inverter 3, the first 4 and second 5 drivers, the error counter 6, the first 7 and second 8 elements of the match.

The proposed device works as follows.

The received information pulse sequence arrives from the device input to the second input of the I-shift register and is advanced in it using clock pulses. The same sequence is fed to the third input of shift register 1 via inverter 3. The signal from inverter 3 writes off the number recorded in shift register I as the information sequence advances in it. Thus, in the absence of interference, when the duration of a signal of one polarity is equal to the duration of a signal of another polarity, i.e. the number of elements of a positive polarity signal recorded in shift register 1, is equal to the number of erasable elements of a negative polarity signal, then the error signal the output of shift register 1 does not appear.

Error detection in a linear signal, caused by the action of positive polarity interferences, is performed using the shift register 1. In this case, the positive impulse is longer in duration than the negative impulse, T; e. the number of positive polarity signal elements recorded in shift register 1 is greater than the number of negative polarity signal emitters and the output of shift register 1 is an error signal that goes to the inputs of the error counter 6 and the first imager 4. Formed the reset signal from the output of shaper 4 sets the shift register 1 to the initial state. The detection of errors caused by the action of bipolar interference in the pauses between signals or messages is performed using the coincidence element 7. The first additional output of shift register 1 is the output of successive bits, and the second additional output is the inverse output of the subsequent discharge corresponding to the minimum duration of the positive pulse of the bi-pulse signal. During the action time of the positive-polarity interference in the shift register 1, a number is recorded and on the first additional output of the shift register 1 a signal appears "1", which is fed to the first input of the coincidence element 7. Since the duration of the interference does not reach the minimum

the duration of the information pulse, from the secondary auxiliary output of the shift register 1 to the second input of the coincidence element 7 also receives the signal "1. Interference without reaching minimum duration

information pulse, changes its polarity to negative, which means that the signal "1" appears at the output of the inverter 3, which arrives at the third input of the coincidence element 7 and forms its output

signal “error, which is fed to the first auxiliary input of the error counter b.

Error detection in a linear signal caused by the action of negative polarity interferences occurs similarly to

using the second shift register 2 and the second match element 8.

Therefore, the use of new elements and connections allows to increase the reliability of error detection in the occupied linear path during transmission by the bi-pulse code.

The technical and economic effect of using the proposed device consists in increasing the reliability of measuring information represented by bi-pulse signals in the occupied linear path by detecting errors when the bipolar interference is affected by the indicated signals regardless of the time of their occurrence.

Claims (1)

Invention Formula A device for determining the reliability of information on the author. St. No. 522550, characterized in that, for the purpose of boosting. Accuracy of determining the reliability of information transmitted by bi-pulse signals, introduced the first and second elements of the match, while the first and second additional outputs of the first shift register are connected respectively to the first and second inputs of the first match element, the third input and output of which are connected respectively to the output of the inverter and to the first an additional input of the error counter, and the first and second additional outputs of the second shift register are connected respectively to the first and second inputs of the second element A match, the third input and output of which are connected respectively to the input of the inverter and to the second additional input of the error counter. Information sources, taken into account during the examination 1. USSR Copyright Certificate No. 522550, cl. H 04 L 1/10, 1975.