SU807279A1 - Multiplying device - Google Patents

Description

The invention relates to digital computing and can be used in digital computers. Multiplication devices are known that contain shift registers, a transmission block, And 1 elements. However, a reduction in the calculation error in these devices is provided by introducing additional bits into the registers and adders or by introducing random number sensors, which leads to a decrease in speed and an increase in hardware costs. The closest in technical essence to the present invention is a multiplication device, containing the first and second shift registers, the adder, the transmission gates ,. The first element is AND (53 This device has a simple design, but its computational accuracy is low because the instrumental calculation error caused by the shift of the multiplicand to the right is proportional to the bit size. To achieve the computation error less than the low-order unit, the device contains additional bits of the first register and an adder, which leads to an increase in hardware costs and a decrease in speed. The aim of the invention is to reduce the computation error. l is achieved by the fact that the multiplier containing the first and second shift registers, the adder, the block of transmission units, the first element I, and the outputs of the first register through the block of transmission elements and transmission are connected to the inputs of the accumulator, the first input of the first element, And is connected to the input device, the second input - with the output of the first bit of the second register, and the output - with the control of the inputs of the block of elements of the transfer, introduced the second element, the first input of which is connected to the input of the device, the second input - with the output of the second bit of the second th register / third input - to the output of the last discharge of the first register, and an output with the input of the adder discharge. The drawing shows a block diagram of the proposed device. The device contains the first and second registers 1 and 2 of the shift, respectively, the adder 3, the block 4 elements And transmission, the first 5 and second b elements I.. The device performs a multiply operation with higher bits forward with a shift of the multiplier to the left, and a multiplicative - to the right. The source data for the multiplication of the multiplier A 1 and the multiplier B 1 is entered in the first and second registers 1 and 2, respectively. The device operates cyclically. In each cycle, the multiplicand, initially equal to A, is shifted by one bit to the right in the first register 1, and the multiplier, initially different. B is shifted one bit to the left in the second register 2. Under the influence of the control signal applied to the device 7, the next digit of the multiplier from the first output of the second register 2 through the first element 5 goes to the control inputs of the block 4 of the elements AND transmission . If this digit is equal to one (zero), then the transfer occurs (does not occur), then the multiplicand from the first register 1 is shifted through the block of 4 elements AND transfer. To the adder 3. At the same time, under the influence of the same control signal by the second element And 6, the multiplication and multiplication of the product of the multiplier () is taken from the second bit of the second register and the multiplier number taken from the last bit of the first register 1 to the last bit of the adder 3. After the end of the nth a cycle, where n is the device spacing, in the adder a voltage is formed Production C A B. When analyzing the computation errors, the counts are uniformly equal to the occurrences of zeros and ones in the bits of partial products. As a result of multiplying two numbers n,; p A rt 2: a: 2 i i. And D 51 JM where, b; , e Go, 1 digits of multiplier and multiplier, respectively, n -. width, we obtain the product 4 Z b: 2- s: where, 1 is the digit of the product. In general, in partial n cycles, all partial products are beyond the size of the first register bit grid, i.e. in (n + 1) -o (p. + 2) -th, ..., 2n-th bit, will not participate in the formation of prod. keeping, i.e., their sum, taking into account the weights of the bits, gives an instrumental error due to the shift of the multiplicand to the right, which has a minus sign, since the product is obtained with a disadvantage. In this device IB, each cycle under the influence of the control signal supplied to the device 7 by means of the second element Ib, the I is generated and I transmit the product of the multiplier number taken from the second bit of the second register 2 and the multiplicand number taken from the last bit of the first p (gistr "1, last bit amount: ora 3. This means that all the (n + 1) -s partial products of I are added to the n-th partial products, i.e. (n + 1) -th part works double, and the values (n + + 2) -th, (n + and so on | D. partial The known standard error is 6 i - (p-1) / 3- 2 where D is the variance of the instrumental error. For the proposed device, the corresponding average error is 6 47. nflTTC is a comparison of expressions (1) and ( 2) Allows to draw conclusions. 1. The magnitude of the calculation error of the proposed device is less: the magnitude of the calculation error of the known device. 2. The magnitude of the calculation error, expressed in terms of the fallen bit, does not depend on the size of the number representation for the proposed device. 3. The magnitude of the computational error, expressed in the units of the shaded discharge, increases with the error: the value of the size for the known device. 4. The value of the mean square error of the calculations of the proposed device 3 OC / (times less than the root mean square error of the calculations of the known device, i.e. OS 4 (n-1) / 2. For different values of η the relative reduction of the standard error of the calculations of the proposed device compared to with a known device about is summarized in Table 1.

Table 1

The bit depth (n) is 8 16 24 32. 40 48 56

RMS error S) 1.87 2.74 3.39 3.94 4.42 4.85 5.24

To achieve the magnitude of the computational error, which is less than one billion-bit unit, as in the proposed device, the first register 1 and the sum 3p need to enter k logg (n-k) additional bits in the well-known device.

The introduction of additional bits leads to an increase in hardware costs and to a decrease in speed

81624

345. 1.38 1.25 1.21

The effectiveness of the invention is to reduce the calculus accuracy, expressed in units of the least significant bit due to a decrease in instrumental accuracy due to the multiplicand shift to the right, depending on the size of the device.

Claims (2)

Invention Formula A device for multiplying, containing the first and second register shift, an adder, a block of transmissions, a first element and, with the outputs of the first register through the block of transmission elements And connected to the inputs of the adder, the first input of the first element And connected to the input of the device, the second input - with the release of the first discharge 64 5.61 5 | (n4-k) / n 1 + k / n times in comparison with the proposed device. For various values, the number of additional bits and the ratio of the relative increase in speed and decrease in hardware costs of the proposed device as compared with the known device are shown in Table. 2 Table 2 32 40 48 56 64 5 6 1.16 1.15 1.13 1.11. 1.09 A second register and an output with control inputs of a block of elements And a ped ped, characterized in that, in order to reduce the calculation error, a second element I is entered into the device, the first input of which is connected to the input of the device, the second input - with the output of the second bit of the second register, the third input - with the output of the last bit of the first register, and the output - with the input of the last bit of the adder. Sources of information, taken into account during the examination 1. USSR author's certificate 442472, CL. G About F 7/39, 1974.. 2. Papernov A.A. Logical bases of digital computing technology, M., Soviet radio, 1972, p. 199, fig. 3 (prototype).