SU794756A1 - Device for correcting error packets - Google Patents

Description

one

The invention relates to communication technology and can be used in the construction of data transmission systems.

A device for error packet correction is known, comprising on the transmitting side a matching unit, a stochastic transducer and a sensor of first-stage check combinations, and on the receiving side serially connected matching unit, a stochastic transducer, a drive and the first block of elements AND, and the bit inputs of the accumulator are connected to the outputs the second block of elements And 1.

However, such a device has a low correction accuracy.

The purpose of the invention is to improve the accuracy of error correction.

For this, the error correction device containing on the transmitting side a matching unit, a stochastic transducer and a sensor of the first-stage check combinations, and a serially connected matching unit on the receiving side, a stochastic transducer, a drive and the first block of elements AND, and the bit inputs of the accumulator are connected with the outputs of the second block of elements And, on the transmitting side, a shaper of test combinations of the second stage is introduced, and the output of the matching block is connected stochastic input transducer directly and via a series

the connected shaper of the second-stage check combinations and the sensor of the check combinations, and at the receiving side, a sub-block sampling register and a series-connected shaper of the reference sequence, an analyzer and a sub-block correction block are entered, the outputs of the first AND block are connected to the shaper selector inputs, and another analyzer output through the sub sampling register is connected to the other inputs of the first and second blocks of the AND elements, other bit outputs of the storage ring Connected to the other inputs of the sub-block correction block, the reference sequence generator consists of an erase register and a sample selection register, whose outputs are connected to the inputs of the AND block, the inputs and outputs of the register

The modulation and sampling register of the reference and the outputs of the block of elements Il are respectively the inputs and outputs of the generator of the reference sequence, and the analyzer consists of serially connected), and the test combination, block of comparison, control unit, first key and comparison register, as well as the second key, the inputs of which are connected respectively to the second outputs of the register of check combinations and the control unit, the input of which is connected to another input of the first key, and the output of the register of the comparison is connected to g The other input of the comparison unit, the other input and output of the comparison register, the input of the register of check combinations, as well as the third and fourth outputs of the control unit and the output of the second key are respectively the inputs and outputs of the analyzer.

FIG. 1 and 2 are given the structural electrical circuit of the proposed device.

The device contains on the transmitting side the matching unit 1, the stochastic converter 2, the sensor 3 of the first stage check combinations, the shaper 4 of the second stage check combinations, and on the receiving side the matching unit 5, the stochastic converter 6, drive 7, blocks 8 and 9 of the And elements, register 10 samples of sub-blocks, generator 11 of the reference sequence, analyzer 12, sub-block correction block 13.

The reference sequence generator 11 consists of an erase register 14, a sample selection register 15, a block of 16 elements I. The analyzer 12 consists of a check combination register 17, a comparison block 18, a control block 19, keys 20 and 21, and a comparison register 22. Unit 13 consists of a register 23 of the second stage verification code symbol, accumulator 24 and decoder 25.

The device works as follows.

A code block with a length of N characters coming to block 1 is divided into sub blocks of ki symbols each, which are then output to shaper 4, where they receive redundant second stage code symbols as k blocks of g characters in the number g and write them to shaper 4, represented which is a circular shift register. The information sequence is received by the subblocks with the length ki of characters into the stochastic converter 2. At the same time, the TI of the check pattern symbols are part of the sensor 3 of the driver 4, which is part of the check code of the second stage.

After the stochastic transformation of the obtained sub-block of the first stage, consisting of fii symbols, of which / r, information, and () check, is transmitted to the communication channel. At this time, the next information subblock of length k arrives in the stochastic converter 2; characters, and in sensor 3, the next part of the second stage check symbol of the second stage of character g is output from shaper 4, and so on.

Thus, 5 sub-blocks of the first-stage code will be transmitted to the communication channel, each of which contains k informational and Γ verification symbols, and each verification combination is part of the verification symbol-and the second

Stage 10 — repeats when transmitting through G2 sub-blocks t times.

At the receiving side, after the inverse stochastic transformation, each received subunit of length n is recorded 15 into accumulator 7. After filling in accumulator 7 (receiving kz subblocks) unit 18 writes signal "1 to register 10, which is a G2-bit shift register. The signal from the first bit of register 10 is fed to the corresponding inputs of block 9 of elements H, to the inputs of which the outputs of accumulator 7 are connected, which ensures writing to register 14 of accumulator 7 t subblocks that have the same test combinations of the same part of one of the test symbols second stage code.

In the initial state, the first bit of register 10, made in the form of an annular shift register, is recorded as "1. After register 14 is filled by a signal from register 10, fed to the nerve input of the block 16, elements And, to the second inputs of which are connected the outputs of register 14, in

5, register 17 records the check symbols of the first sub-block, and register 22 begins alternately on the signals from block 19 to receive sub-blocks from register 14. Block 18 compares the test combinations of each of the sub-blocks, which are alternately written to register 22, with the check pattern written in register 17, in this case, the first step of the unit. From register 22, sub-blocks are again entered into register 14.

If the values of the verification combinations of the sub-blocks coincide with those recorded in the register 17, the 18-block of the .block 19 will be issued / signals “correctly, which means that

0 register 17 recorded value, which will be for the standard. The control unit 19 stops the comparison operation and returns the register 14 to its initial state by a series of pushing pulses. After that, the signals from block 19 check combinations of t sub-blocks from register 14 are compared with the standard recorded in register 17 when the compared combinations do not match, the error signal from block 18 through key 21, to the second input of which unlocking voltage is applied from the block 19, erasure of the sub-block occurs, which is located in register 22.

5 After comparing all the sub-blocks re: the gistr 14 will be filled with sub-blocks received correctly (with an undetected error) and erase signals in place of the distorted sub-blocks. By a signal from block 19, information subblock combinations received correctly, and erase signals are recorded in drive 7 at locations determined by block 8 of elements AND, the second inputs of which are connected to outputs of register 10, in the first bit of which "1. The combination of register 17 through the key 20, to the second input of which the unlocking signal from block 19 is fed, is entered into register 23, after filling in which the combination recorded in it, i.e. the check code symbol of the second stage, consisting of several parts - check combinations sub-blocks of the first stage will be output to the accumulator 24. Block 19 generates a signal, according to which "1 register 10 is rewritten into the next bit and into register 14 through block 9 elements I receive the following t sub-blocks having the same test combinations on transmission ii and t. d.

if, when comparing the verification combinations / sub-blocks of the first-stage code recorded in register 14 with the combination in register 17, from block 18 to block 19 does not arrive / signals “true, then from block 19” 1 will be rewritten into the following bit of register 15, and a check combination of the next sub-block from register 14 will be issued to register 17. If, however, t sub-blocks recorded in register 14 do not have the same check combinations, i.e., if t cycles of comparison operations are performed, the block 19 there were no signals “right, then the signals from Lok 19 the contents of register 14 and register 23 is erased and the corresponding storage space 24 7N signals "erase written. After filling the accumulators 7 and 24, the block 19 rewrites the check and information symbols of the code of the second stage, as well as the erase signals to the decoder 25, where the erasures are erased.

The proposed device improves correction accuracy.

Claims (3)

1. A device for correcting error packets, containing on the transmitting side a matching unit, a stochastic transducer and a sensor of first-stage test combinations, and on the receiving side serially connected unit consistency, stochastic transformation | azoatel, storage device and first block of elements And, and the bit inputs accumulate connected to the outputs of the second block The elements And, differing from the fact that, in order to improve the accuracy of correction of error packets, a shaper of second-stage check combinations is inserted on the transmitting side, the output of the matching unit is connected to the inputs of the stochastic converter directly and through the sequentially connected shaper of second-stage check combinations and a sensor of check combinations, and on the receiving side, the sub-block sampling register and the sequentially connected reference sequence generator, the analyzer and the sub-block correction block are entered, the outputs of the first block of elements I are connected to the inputs of the reference sequence generator, and the other output of the analyzer is connected to the other inputs of the first and second blocks of elements And, the other bit outputs of the accumulator are connected to the other inputs of the sub block correction unit. 2. A device according to claim I, characterized in that the reference sequence generator consists of an erase register and a sample selection register whose outputs are connected to the inputs of the AND block, the inputs and outputs of the erase register and the register of the reference sample, and the outputs of the AND block are respectively inputs and outputs of the master reference sequence. 3. A device according to claim 1, characterized in that the analyzer consists of a serially connected register of a check combination, a comparison unit, a control unit, a first key and a comparison register, as well as a second key whose inputs are connected respectively to the second outputs of the register of checking combinations and block the control, whose input is connected to another input of the first key, and the output of the comparison register is connected to another input of the comparison unit, others the input and output of the comparison register, the input of the register of check combinations, as well as the third and fourth outputs of the control unit and the output of the second key are respectively analyzer inputs and outputs. Sources of information taken into account in the examination 1. USSR author's certificate in application number 2461681 / 18-09, cl. H 04 L 1/10, 1977 (prototype).