SU911613A2 - Device for recording and checking programmable fixed storage units - Google Patents

Description

(5) DEVICE FOR RECORDING AND CONTROL OF PROGRAMMABLE UNITS OF CONSTANT MEMORY

This invention relates to memory devices.

According to the main author. St. No. 796909 a device is known for recording and monitoring programmable blocks of permanent memory, which contains a current address register and a data register, one of the inputs of which is connected to the outputs of the master oscillator and the operative memory block, and the outputs respectively to the first outputs of the address forwarder and a data signal generator, a final address comparator, whose inputs are connected to the outputs of the final address register and the current address register, a data comparator, one of the inputs of which is connected to the input of the device TWA and the other inputs are connected to the outputs of the data register and the main memory unit, one of the inputs of which is connected to the output of the counter, the control unit, the analog memory unit, keys, digital-analogue

a converter, a decoder, an additional memory unit and a counter, a synchro shaper and a programmable sync block, the inputs of the analog memory block are connected to the key outputs, and the outputs - with the second inputs of the address signal generator and the data signal generator and the first input of the sync signal generator, the second input of which is connected to the output of the block of programmable sync signals and other inputs of the current address register and the data register, and the output to one of the outputs of the device, you decoder and digital-analogue moves. the converter is connected to the key inputs, and the inputs are respectively to the outputs of the additional counter and the additional RAM block, the first input of which is connected to the output of the additional counter, the output of the control unit is connected to the 39 input of the additional counter, the second input of the additional RAM block and one from the block inputs of programmable clock pulses, another input of which is connected to the output of the master oscillator Cl. The disadvantage of this device is that in the case of functional control of programmable blocks of constant memory with a volume of 6-6 i) thousand or more words, it is necessary to have a large-capacity RAM memory as part of the device. The presence of such a unit as part of a device significantly complicates the equipment and reduces the reliability of the device. The purpose of the invention is to increase the reliability of the device. This goal is achieved by the fact that the device contains a shift register, a driver of control signals and an adder, with the first inputs of the shift register and adder being connected to one of the device inputs, the CTO inputs to the driver output. control signals, the input of which is connected to one of the outputs of the control unit, the third input of the adder is connected to the output of the shift register, and the output of the adder is connected to one of the data comparator inputs, the other input of which is connected to the output of the control signaling unit. The drawing shows a block diagram of a device for recording and monitoring programmable blocks of a permanent memory. . The device contains a control unit 1, a current address register 2, an end address register 3, a data register, a master oscillator 5, a random access memory block 6, a counter 7, an end address comparator 8, a data comparator 9. An individual module 10 is connected to the inputs and outputs of the device, to which the programmable fixed memory unit 12 is connected via connectors 11. The device also contains an analog memory block 13, keys I, a decryption tor 15 an additional operative memory block 16, a counter 17. a digital-to-analog converter 18, a shaper of address signals, a shaper of 20 data signals, a shaper of clock signals, a block of 22 programmable sync signals, sum4. the mat 23, the shift register and the driver 25 of the control signals. The first inputs of the shift register and the adder 23 are connected to one of the device inputs, the second inputs to the output of the driver 25, the input of which is connected to one of the outputs of the control unit 1. The third input of the adder 23 is connected to the output of the shift register 24, and the output of the adder 23 is connected to one of the inputs of the data comparator 9, the other input of which is connected to the output of the former 25. The device works as follows. The memory of block 1 records the primary control programs with the help of which the quality of block 12 is determined. From block 1 in accordance with the input control program, information is required is entered into the operational memory block 16 to set the value of the upper and lower limits of the pulses of the formers 19 to determine the beginning and end of control; in block 22 of programmable sync signals to select the channel number, delay and duration of synchronization pulses; in the master oscillator 5 defining the frequency control. Upon a command from block 1, in accordance with the time diagram of block 12 operation, block 22 outputs signals to individual module 10 and registers 2 and 4. At the initial address recorded in register 2, information from block 12 is read to comparator 9 where it is compared with the contents register t. A positive comparison result allows the unit to be added to register 2 with a period determined by master oscillator 5. A negative comparison result goes to block 1 and it is forbidden to add one to register 2. When comparing the contents of register 2 with the contents of the register 3, block 1 receives the Fit command. The formation of the magnitude of the upper and lower limits of the pulses in the former occurs after writing in the block 16 of the last word. The counter 17 is activated by its own internal generator. Each state of the counter 17 is decoded by the decoder 15 into a positional code and the reading of the corresponding word as a binary code from block 16. 5 The binary code of each word of block 16 is converted by a digital-to-analog converter 18 to an analog signal. This signal, through an open corresponding positional code of the decoder 15, one of the keys 1 4 arrives and is stored by the memory elements of the block 13 of the analog memory. From the outputs of block 13, the corresponding voltage cvir voltages are fed to the formers 19–21, preparing them for operation. After preparing the drivers from register 2, the addresses 19 of the cells of block 12 are sequentially received. They, transforming the formers 19 into the required form, arrive at the address inputs of block 12. With the code of each address of block 12, a control signal is output by the block 22. This signal shaper 21 also enters the corresponding inputs of block 12. At each address, the information of the selected cell of block 12 is read and this information is compared with the initial written in the first page C comparator 9. So continue This is until the register code 2 is compared with the register code 3 by comparator 8, which outputs the corresponding signal to block 1. The cycle of the input health check block 12 ends. This is how the functional control cycle of blocks 12 with a volume of up to -16 t1c is performed. bit information of If the volume of block 12 is greater than the specified value, then their primary functional control can be performed according to an abbreviated program with the help of adder 23, register 2k and shaper 25. To this end, preparation of all blocks and nodes of the device is carried out similarly to that described above. The entire memory array of block 12 is divided into several zones. For each zone, a cyclic or ordinary sum of the numbers included in that zone is determined. In block 6 of the RAM, the values of the indicated amounts are entered. In the case when block 12 has one bit, shaper 25 blocks comparator 9 and adder 23 opens register 2C to receive information from block 12. At the same time register 2 is filled. Then shaper 25 generates a signal to transmit information from register 2 to the adder 23. The number 3.6 transferred from the register 2+ to the contents of the adder 23 is summed. The described operation cycle continues until the last number from the monitored memory zone of the block 12 is read and the sum of all the numbers in the zone is received. . After that, the imaging unit 25 transmits the obtained amount to the comparator 9, where the control number was earlier from the 6-RAM memory unit. The check number is entered and where they are compared and the result of the control is determined. The control cycle of the next zone of block 12 is similar. In the case when multi-block 12 is monitored, information can be transmitted directly to adder 23, mine register 2. In accumulator 23, the sum of the numbers of the controlled zone of block 12 accumulates. The subsequent monitoring cycle is similar to that described above. After the input functional control is performed, programming (recording) is performed in accordance with the truth table stored in the memory of block 1. To this end, after entering the required information and preparing for operation of the formatter 19 21 similar to that described above from register k to the driver 20, synchronously with each the address receives information, according to which the electrical programming of the block 12 takes place. The differences between the programming mode and the input control mode are the following: adding a unit to register 2 of the wire ITS team from Block 1, and. not from the master oscillator from the synchronization channels is selected to organize a pause after programming, since, for example, bipolar circuits of programmable permanent memory blocks require a significant pause after programming each bit in the programming mode during the pause, the correctness of programming is checked depending on the type of circuit programmable block 12 after each bit or the entire word, the master oscillator is needed only for the organization of clock pulses and a pause in block 22. Program mode ovani performs, as in the first case, to those

7

until register code 2 equals register code 3.

After completion of the programming mode, the output function control mode is conducted. The differences in the output control mode from the input one are that the expected information for comparison when reading from block 12 to comparator 9 comes from operating memory block 6, which was previously entered from block 1; adding one to counter 7 and register 2 goes synchronously from the master oscillator 5 with a frequency limit for a specific type of block 12; if the memory capacity of block 6 is less than the volume of memory of block 12, the output function control mode is repeated several times, the successive register 2 is increased sequentially. The end of the output function control is carried out according to the contents of register Zn

The output functional control of programmable permanent memory blocks with a large memory capacity can; also be done by comparing the control amounts as described above in the input control section.

The proposed device allows to perform functional control.

16138

blocks of permanent memory with a volume of more than 16-65 thousand bits of information with limited (2 thousand bits) volume of the RAM block of the device itself.

Formula inventions

A device for recording and monitoring programmable blocks of the permanent memory according to the autor.ev 79690S. characterized in that, in order to increase the reliability of the device,

it contains the shift register, the driver of the control signals and the adder, with the first inputs of the shift register and the summatr connected to the device from the inputs of the device, the second

inputs - to the output of the driver control signals, the input of which is connected to one of the outputs of the control unit, the third input of the adder is connected to the output of the shift register, and the output

The adder is connected to one of the data comparator inputs, the other input of which is connected to the output of the control signal generator.

Information sources,

taken into account in the examination

1. USSR author's certificate No. 796909, cl. 6 11 С 7/00, G 11 С 29/00, 01.20.78 (prototype).

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Claims (1)

Claim A device for recording and monitoring programmable read-only memory blocks by auth. 796909, characterized in that, in order to increase the reliability of the device, 1S it contains a shift register, a driver of control signals and an adder, the first inputs of the shift register and adder connected to the back of the device inputs, the second 20 inputs to the output of the driver of control signals, the input of which is connected to one of the outputs of the control unit, the third input of the adder is connected to the output of the shift register, and the output 25 of the adder is connected to one of the inputs of the data comparator, the other input of which is connected to the output of the driver of control signals.