SU767990A1 - Device for detecting m-trains - Google Patents

Description

(54) DEVICE FOR DETECTION OF M-SEQUENCES

one

The invention relates to a rasmotehnike and can be used asynchronous address communication systems, as well as in instrumentation equipment .5

A device for detecting M-sequences is known, comprising a series-connected clock generator, a buffer shift register and a CLI-NE element, and, O, therefore connected a decisive shift register, a block of AND blocks and a modulo two, while the outputs of other bits buffer shift register connected to another 15 inputs of the block of elements And 1.

However, the accuracy of detection of M-sequences in a known device is low.

The purpose of the invention is to increase the accuracy of detection of M-sequences.

For this, a switch 25 connected in series, controlled by a control unit, a check shift register, an error analyzer and a recorder, are entered into a known device for detecting M-sequences. In addition, the output of the clock generator is connected to control inputs 30.

check register shift and switch, to the other inputs of which are connected respectively the outputs of the element ILT-NOT and the adder mod. G. two, and the other outputs of the switch are connected to the corresponding inputs of the solving shift register, to the other inputs of which the output of the error analyzer is connected and the registrar is connected to the outputs of the decisive shift register.

In this case, the error analyzer consists of the AND elements, the block of the AND elements, and the OR-NOT element, the outputs of which are connected to the corresponding inputs of the OR element, whose output is the output of the error analyzer.

The drawing shows a structural electrical circuit of the proposed device.

Device for detecting M-sequences contains

1-stroke pulses buffer register

2 shift, the element OR-NOT 3, the switch 4, containing two blocks 5, 6, the decisive shift register 7, the block of elements AND 8, the adder 9 modulo two, the recorder 1o, the control block 11,

767990

a calibration shift register 12 and an error error indicator 13, containing the block of elements AND 14, the element IDI-NOT 15, AND 16 and the element OR 17.

The device works as follows.

In the INITIAL state, switch 4 disconnects its outputs from the inputs. All cells of buffer 2, decision 7, and check 12 shift registers are zero, with the exception of the input cell of decision shift register 7, the state of which corresponds to logical 1. The received sequence is written to buffer shift register 2. Using the item. OR NO 3 on the sequence is detected by a series of (n-1) zeros. When such a series appears, a pulse from the output of the element OR NO 3 connects the output of block 5 of switch 4 to its input, and the output of block 6 to its input, which connected to the input of the decisive register 7 shift. .

As a result, the clock pulses from the generator 1 begin to flow to the decision shift register 7 and the control block 11, which after each (n-1) pulses sends control pulses to switch 4. In addition, a decisive shift register 7 feedback circuit, an AND 8 block, an adder 9 and a block 6 of the switch 4, closes and the solution of the system of linear difference equations begins. The solution is implemented by (n-1) multiplying the advancement of the symbols of the buffer shift register and the critical shift register with the feedback loop of the latter.

Next, the device provides for checking the correctness of the determination of the coefficients of the generator polynomial b | . This is done as follows o6pa3ONi. The control pulse from the output of block 11 enters the second control inputs of blocks 5, 6 of switch 4. At the same time, the output of block 5 is disconnected from its input, and the informational input of block 6 is connected to an output connected to the input of pro-v-v shift register 12. With each further prodizhenii.symbolov in the buffer register 2 shift. ha entry check Key register 12 shift-will be.-step test. Symbol b, formed by using b Element block. And 8 and adder 9. ;; l.- ; . -

After n advances, the check register 12 of the shift will be completely filled with the symbols b, With the correct determination of the coefficients;, an undistorted M-sequence can be assumed. In this case, the characters, O for all f,. That are found in. element OR NOT 15.. Na; ps: Immediately a segmente can be one of the symbols, msk sen

wherein the state of the cells of the check register 12 shift repeats the state of the cells of the solving shift register 7, which is detected by means of an AND 14 block.

5, the M-sequence may be used as a pseudo-random carrier. At the same time, its symbols can be inverted by the law, the information sequence. As a result, the check symbols can take the value bj, 1, which is detected by the AND 16 element.

Thus, if the state of the cells of the check register 12 shift corresponds to one of the indicated

5 cases, then an output pulse is generated at the output of the element OR 17, which permits the recording of the coefficients h.j to the recorder 10.

If the coefficients are incorrectly determined (and, therefore, the subscriber's address), they are not allowed to be recorded in the recorder 10.

Thus, the introduction of new elements allows for verification

5 the correctness of the determination of the coefficients of the generator polynomial of M-sequences, and therefore, improve the reliability of the device.

Claims (1)

1. A device for detecting M-tio sequences containing serially connected clock generator, buffer shift register and. the element OR-NOT and serially connected decisive shift register, the block of elements AND and the adder modulo two, while the outputs of the other bits of the buffer shift register are connected to the other inputs of the block of elements I, O m and-h with the fact that, in order to improve the accuracy detection of M-sequences introduced sequence | but connected by a KoNJMyTaTOp, controlled by a control unit, a test shift register, an Errorr analyzer and a recorder, with In this case, the output of the clock pulse clock is connected to the control inputs of the check shift register and commutator. k. to the other vkhddam.kryogo connected to the answer of the appearance of the element OR-NEL modulo modulator two, and the other outputs are commutative 4t.op preparation (very K; corresponding, vukitsim. entry register decisive register - food, .. to - OTHERS; KQTOporp inputs. An analyzer-error output is connected to,) in: which 4Dam and the registrar are connected the outputs of the decisive shift register i. .- ,. ; . , 2. The device according to claim 1, of which is, the error angrhizator consists of the units along the inputs of the AND element, the AND block, and the OR-NOT element, whose outputs connected to the corresponding inputs of the OR element, the output of which is the output of the error analyzer. Sources of information taken into account during the examination 1. GAI-BIN GO., Ward R. B. Methods for decoding the sequence of maximum length, TIIER, vol. 65, 7, 1977 (prototype).