SU794728A1 - Decoding device with error correction - Google Patents

Description

one

The invention relates to computing, can be used in devices for detecting and correcting single and group errors when monitoring the storage and transmission of discrete information.

A decoder with error correction is known, which contains a data register whose output is connected to the input of the pilot bits generator and the first input of the correction adder block, while the outputs of the pilot bits generator are connected to the first inputs of the adders of the first and second groups of test bits, to the second inputs which are connected, respectively, the outputs of the registers of the first and second groups of test bits 1.

However, the known device is complicated and has a low decoding accuracy.

The purpose of the invention is to improve the decoding accuracy and simplify the device.

For this, an error-correcting decoding device containing a data register, the output of which is connected to the input of the pilot bits generator and the first input of the correction adder block, and the outputs of the pilot bits generator are connected to the first inputs of the first and second groups of adders.

the control bits, to the second inputs of which are connected respectively the outputs of the registers of the first and second groups of control bits, are entered in series with a return decoder, a unit for multiplying two quantities, a decoder for the position error number, and a valve block, the output of which is connected to the second input of the correction adder unit, the output of the adder of the first group of check bits is connected to the second input of the valve block, and the output of the adder of the second group of check bits is connected to the second input do decoder number erroneous position.

The drawing shows a structural electrical circuit of the proposed device.

The device contains the data register 1, the register 2 of the first group of test bits, the register 3 of the second group of test bits, the former 4 test bits, adders 5 of the first group

check bits, adders 6 of the second group of check bits, a decoder 7 of the return value, a block 8 multiplying two values, a decoder 9 number of an erroneous position, a block 10 of gates and a block AND

correction adders. The outputs of the correction adder unit are device outputs.

The device works as follows.

At the inputs of the imaging unit 4, there are n characters (groups) with m bits each, from the outputs of register 1, where the control bits are formed, which are then summed on adders 5 and 6 to the contents of registers 2 and 3. If in one of the groups of register 1 Any error occurred, the outputs of the adders 5 and 6 will be different from zero, and the outputs of the adder 5 will show the magnitude of the error bg. and the outputs of the adder 6 - the product of the error on the number of the position in which it occurred, i.e. On the decoder 7, the reverse value of the error bg is formed, and on block 8 - the position number at which the error occurred. The position number is decrypted on the decoder 9. The signals from the decoder 9 allow the error value from the outputs of the adders 5 through block 10 to be summed up at block 11 with the faulty group of register bits 1. The remaining groups of bits of register 1 are summed with zero at block 11.

Introduction to the device of the decoder 7, 1 block 8, the decoder 9 and the block 10 allows to significantly increase the reliability and reduce the equipment of the device.

Claims (1)

1. Francis TA, Yanbykh G. F. Redundancy in electronic devices. L., “Energie, 1969, p. 227-235. W 1  S.I f JuL.