SU792250A1 - Monitored arithmetic unit - Google Patents

Description

The invention relates to the field of computing and can be used to control arithmetic devices. Devices 1, 2 are known that control arithmetic devices based on the principles of parity and residue control. The disadvantage of such devices is limited control. The closest in technical essence to the proposed is. controlled arithmetic unit 3, Received for a prototype containing the first and second registers of operands, the inputs of which are connected to the corresponding information inputs of the device, and the outputs to the corresponding inputs of the adder, connected to the result register and the first information input of the code comparison block. The disadvantage of this device lies in the low reliability of the control unit. The purpose of the invention is to increase the availability of control devices. This goal is achieved in that the device contains a block of logical addition of operands, a block of OR elements and a block of NAND elements, whose inputs are connected to the corresponding inputs of the block of OR elements and. with the corresponding inputs of the adder, and the output with the second information input of the first register of operands, the output of the result register is connected to the second information input of the second register of operands, the output of the block of elements OR through the block of logical addition of operands to the second information input of the code comparison block .. Structural The scheme of the arithmetic unit with the control is shown in the drawing. It contains the first 1 and second 2 registers of operands, the result register 3, sukv-iaTOp 4, buses 5 and 6 operands, block 7 of the elements OR, block 8 of the elements of NAND, block 9 of the incremental logical addition of operands, block 10 of the comparison of codes, bus 11 control. The synchronization and clocking chains are not shown in the diagram. The principle of operation of the device is that, if the adder is functioning properly, the bit sum of the logical sum of the input operands must be equal to the difference of their arithmetic sum and bit code of the same operands. Hence, it follows that each working cycle of the programmers of the two operands occurs in two

tact

Addition. Operands on buses 5 and 6 are written to registers 1 and 2. At the output of block 7, a bit of a logical input code is generated, which is written into block 9. At the output of block 8, an inversion of the bit logical product of operands is formed, but it is not recorded in register 1 . From the output of the adder 4, the sum of the operands is entered into the register 3. After the information is entered into the register 3 and block 9, the second cycle of the operating cycle is performed.

Subtraction. In this cycle, register 1 is inverted by bitwise logical product operands. To do this, this register can be executed on triggers with an internal delay. In the same cycle, the information from register 3 is copied to register 2, and bus 11 is used to invert the state in which bus 11 was on the clock. Addition. In other words, in the Subtract cycle, the sum of two operands is added to the additional bit code of the same operands, and after the new value is set at output 4, a comparison is made in Figure 10 of this code with the bit logic sum written earlier in block 9. The equality of these two codes indicates the correct execution of the clock cycle. Addition.

The purpose of the invention is to increase the reliability of the contour i - is achieved

due to the detection of malfunctions of arbitrary multiplicity in the output code of the adder and any constant malfunctions of the device elements due to its significant distinguishing features.

Claims (3)

1. USSR author's certificate  551646, cl. G 06 F 11/04, 1977. 2. Authorship certificate of the USSR No. 297041, cl. G06 F 11/00, 1968. 3. Authors' certificate of the USSR No. 404084, cl. G06 F 11/00, 1975 (prototype).