SU790225A1 - Pulse synchronizing device - Google Patents

Description

The invention relates to a pulse technique and can be used to synchronize devices of automation and computing. A device for synchronizing pulses is known, which contains a trigger connected by one input to a source of input pulses, and another via a delay stage to the output of the device, and a combinational logic circuit connected between the output of the trigger and the output of the device. triggered trigger contains a two-input coincidence circuit connected in series and a trigger with a counting input, and the output of the coincidence circuit connected by one of their outputs to the sync source The downside impulses are connected to the counting input of the trigger ll. The disadvantage of this device is that it cannot receive a series of clock pulses at the output regardless of the moment the device is turned on (for example, by a start command, upon the arrival of a synchronized pulse) and computing as a pulse synchronizer or starting device. A device for synchronization and mycos is known, which contains two triggers, six logical gates And two logical gates. NOT A disadvantage of the known device is the presence of a large amount of equipment, which reduces the reliability of the pulse synchronization device. The purpose of the image is to increase the reliability of the device. This goal is achieved by the fact that in a device for synchronizing pulses, containing two triggers, six AND logic gates, two NOT logic gates, the first inters of the first and second logic elements {5, comrade I are connected to the device input, the Start device is connected to S- the input of the first trigger, the unit output of which is connected to the first inputs of the third and fourth logical elements AND, the output of the fourth logical element AND is connected to the second input of the second logical element AND directly, and through the first logical The second element is NOT - with the second input of the first logical element AND, whose output through the second logical element is NOT connected to the second input of the third logical element AND, the output of which is connected to the second input of the fourth logical element AND, the input of the device Stop connections with the S input of the second trigger , the single output of which is connected to the first input of the fifth logical element AND, the output connected to the R input of the first trigger, and the second input to the output of the second logical element AND whose output is the output of a.

FIG. 1 shows a block diagram of the device; in fig. 2 cyclogram of the device at different points of the triggering and stop signals.

A device for synchronizing pulses contains triggers 1 and 2, logical gates And 3-7, and logical gates 8 and 9.

Before operation, the device is reset, after which it meets the following requirements: it starts only at the moment the Start signal arrives, regardless of the start moment, full-fledged pulses must be generated at the output that coincide in time with the input synchronized pulses in the presence of a Stop signal at the output a single pulse is formed; in the absence of a stop signal, a series of pulses is generated before the arrival of the stop signal.

All of the above modes of operation of the device are explained in the timeline of operation of the device presented in Figure 2.

The device works as follows.

The synchronized pulses supplied to the device input then go to the first inputs of the logical elements AND 3 and 6, however, from the output of the device for synchronizing the pulses; those. the output of the logic element And 6 pulses do not come, because the logical element And 6 is closed by a signal coming from the output of the logic element And 4, which in turn is controlled by the signal coming from the single output of trigger 1. The trigger 1 in the initial state is in zero position, and, therefore, the signal coming from its single arm, closes the logical element And 4, which controls the operation of the logical element And 6.

The trigger 1 is controlled by a start signal, which is fed to the Start input, and goes into one state and a given edge of the start signal.

There are several options for the arrival of the start signal and the end of its trailing edge. All these cases are considered, and the patterns of operation of the synchronization device for these cases are given in FIG. 2.

Consider the case when the start pulse arrives and ends at the pause between synchronized pulses entering the device.

On the trailing edge of the starting impus, the trigger 1 goes into a single state, and the signal that appeared on the unit arm of the trigger 1 enters the second inputs of logic gates And 4 and 5.

Since the ending of the trailing edge of the trigger pulse pauses between the synchronized pulses, the signal coming from the output of the AND 3 logical element through the logical element NOT 9 to the first input of the logical element And 5 coincides in phase with the signal coming from the single output of trigger 1 to the second input of the logic element And 5, the logic element And 5 produces a signal that coincides in phase with the signal coming from the single output of the trigger 1. These signals are connected to the first and second inputs of the logic element And 4 respectively The logical logic element AND 4 generates a signal that, through the logical element NOT 8, arrives at the second input of the logic element 3 and blocks the operation of the logic element 3 from synchronized pulses input to the device. The signal from the output of the logical element FROM, coming through the logical element NOT 9 to the first input of the logical element AND 5, coincides in phase with the signal arriving at the second input of the logical element AND 5, the output from which ensures the operation of the logical element AND L. The logical element AND 4 ensures the operation of the logical element And b,

The synchronized signals entering the device input will be passed to the device output by the logic element Ib until the arrival of the stop signal, on the falling edge of which trigger 2 will enter the single state, the signal from the unit arm 2 will prepare the AND 7 for operation. the output pulse signal from the device (from the output of the AND 6 logic element) on the falling edge translates trigger 1 into the zero state. The logical element AND AND 4 will close and prohibit the operation of the logical element AND 6. The pulses from the output of the device cease.

If the falling edge of the Stop signal occurs at the end of the synchronized pulse coming from the output of the device that is so shortened that the passage through the logic element AND 7 is not able to transfer trigger 1 to the zero state, it will be transferred by the next synchronized pulse. This mode of operation of the device is shown in detail in figure 2a,

In order to ensure the operation of devices in the single-pulse mode, it is necessary that the Stop signal comes and ends earlier than the start signal, otherwise it does not work (the device’s operation is similar to that described above. This device operation mode is shown in detail in figure 26.).

The remaining modes of operation of the device in various situations of arrival of the start and stop signals with respect to the synchronized pulse are shown in detail in figure 2c and 2d.

The use of the proposed device provides, in comparison with known devices, the same modes of operation of a single pulse and a series of pulses at significantly lower equipment costs, which significantly increases the reliability of the device.

Claims (2)

1. USSR author's certificate. № 409353, cl. H 03 K 1/16, 1971. . 2. USSR author's certificate No. 308-513, cl. H 03 K 17/00, 19,69. Iff 11 1 J 9. "-JT -LT five " 8 6 Jl f2 2 7 Jl. ig. 2