SU788419A1 - Morse code shaping device - Google Patents

Description

I

The invention relates to radio engineering and can be used in signal transmission devices, in particular, in Morse code drivers.

A device for generating a Morse code comprising a trigger, an AND-OR element block, a first memory block, an OR main element, a clock generator, an encoder, a start / stop block, the clock generator output connected to the first input of the start-stop block, the corresponding encoder outputs. connected to the first and second inputs of the first memory block 1.

However, the known device does not provide for the formation of a seven-digit telegraph code.

The purpose of the invention is to provide the possibility of forming a seven-digit telegraph code.

To achieve this goal, a signal shaping unit, an additional OR element, an address signal generating unit, a second memory unit, two AND elements, two inverters, a signal inhibiting unit, the first input of which is connected to the first trigger output, are entered into a known device. the block of elements ORI and with the third and memory blocks, the second input of the prohibition block is connected to the fourth input of the block of AND-OR elements and with the output of the start-stop unit, the third input of the prohibition block is connected to the output of the first element AND, the first input which is connected to the output of the second memory block, to the input of the first inverter and to the first input of the main element OR, the second input of the first element AND is connected to the output of the second inverter and to the first input of the second element AND, the second input of which is connected to the output of the first inverter, output The second element AND is connected to the third input of the start-stop unit, the second input of which is connected to the output of the main element OR,

 A swarm whose input is connected to the input of the second inverter and to the output of the first memory block, the fourth input of which is connected to the output of the address signal generation unit and to the fourth input of the second block

20 of the memory, the fifth input of which is connected to the fifth input of the first memory block, to the second output of the trigger and to the third input of the block of the AND-OR elements, the first input of the trigger is connected to the first output of the signal conditioning unit and to the second input of the signal generation unit address, the second input of the trigger is connected to the second output of the code signal generation unit and to the third input of the address signal generation unit, the first input of which is connected to the output of the AND-OR element block, the first input of which is connected to the output of the auxiliary element that OR, whose inputs are connected to the third, fourth, fifth outputs of the signal conditioning unit of the code and the encoder inputs, the corresponding outputs of which are connected to the first and second inputs of the second memory unit, in addition, the sixth output of the signal generation unit of the code is connected to the corresponding inputs the curler. The drawing shows a structural electrical circuit of the proposed device. A device for generating a Morse code contains a trigger 1, a block 2 of the YILI elements, a block 3 of generating address signals, the first memory block 4, (the new element OR 5, the start / stop block 6, the signal inhibitor block 7, the additional element OR 8 the encoder 9, the second block 10 memory, clock pulse generator 11, code signal generation unit 12, first and second inverters 13, 14, respectively, first and second elements 15, 16, respectively. The device operates as follows. In the recording mode, a high level is supplied from the first output of block 12 wives at the first input of trigger 1 and at the second input of block 3. At the same time, from the first output of trigger I, a high voltage level goes to the second input of block 2, allowing passage of a high voltage level from the output of an additional element OR 8 to the first input of block 3. At the same time, high the voltage level goes to the third inputs of blocks 4, 10 and to the first input of block 3. At the same time, a high voltage level goes to the third inputs of blocks 4, 10 and to the first input of block 7, prohibiting the passage of signals to the device output from the second input of block 7. Block 3 is reset and prepares the first memory cells of blocks 4 and 10 for recording. By sending signals from the third, fourth, fifth, and sixth outputs of block 12, the necessary text is written. In the read mode, from the second output of the block 12, a high voltage level is supplied to the third input of the block 3 and to the second input of the trigger 1, while the trigger 1 is set to the zero position and a high voltage level from the second output of the trigger 1 is fed to the third input of the block 2, permitting the passage of a high level of voltage supplied to the fourth input of block 2 from the output of the start-stop block b to the first input of block 3. At the same time, a high voltage level from the second output of trigger 1 goes to the fifth inputs of blocks 4, 10. Block 3 sets c is reset and includes the first cells of the ami blocks 4 and 10. Signals recorded in the first memory cells from the outputs of blocks 4, 10 are fed to the corresponding inputs of the main element OR 5 and to the inverters 13, 14. When reading information With the first memory cell of block 4, a low voltage level is obtained at its output; when reading from the first memory cell of block 10, a high voltage level is obtained at its output. When these signals arrive at the inputs of the main element OR 5, a low voltage level signal is received at its output, which arrives at the second input of the start-stop unit 6. The first input of the start-stop unit 6 from the generator output 11 receives clock pulses with a duration and duty cycle equal to "1 . When applied to the first input of the low-voltage start-stop unit 6, the latter generates one low-voltage impulse and one high-voltage impulse of the corresponding durations, which are fed to the second input of the block 7 and to the fourth input of the block 2. The low voltage signal coming from the output of block 4 to the input of the second inverter I, at the output of the latter, is converted into a high voltage level signal and is supplied in conjunction with a high voltage signal from the output of block 10 to the inputs of the first element 15, to the output which is obtained a high voltage level signal to the third input of the unit 7 and prohibits the passage of conductive signals output from the start-stop block 6 on the output device. At the output of the device, a pause of the total duration is obtained. When a high voltage signal appears at the output of block 4, and at a low voltage level of 10-signal block, the output of the main element OR5 reproduces a low voltage signal, and the start-stop unit 6 generates one low voltage pulse and one a high voltage pulse of corresponding durations, which arrive at the second input of block 7. At the output of the first element 15, a low voltage signal is obtained, which, entering the third input of block 7, permits the passage signals from the start-stop unit 6 output to the device output. A pause and a point or dash signal of corresponding durations are reproduced at the output of the device. After the end of the high voltage signal, the output of the start-stop unit 6 switches the unit 3 and reads information from the following memory cells of blocks 4 and 10. When the read end signal is written, low-level signals appear on the outputs of blocks 4, 10

Claims (1)

Claim An apparatus for generating code ¹⁵ Mor- se, comprising a trigger and or block elements, the first memory unit, or main element, a clock generator, encryptor unit inching, and the output of the clock sub-keys 20 to a first input of start-stop unit, respective outputs the encoder is connected to the first and second inputs of the first memory unit, characterized in that, in order to enable the formation of a seven-digit telegraph code, ^2S introduced the code signal generation unit, an additional OR element, an address signal generation unit, a second memory unit, two AND elements, two inverters, a signal inhibit unit, the first input of which is connected to the first output of the trigger, to the second input of the block of AND-OR elements, and to the third inputs of memory blocks, the second input the inhibit block is connected to the fourth input of the block of AND-OR elements and to the output of the start-stop block, the third input of the inhibit block is connected to the output of the first AND element, the first input of which is connected to the output of the second memory block, to the input of the first inverter and to the first input of the main OR element , the second input of the first element And is connected to the output of the second inverter and to the first input of the second element And, the second input of which is connected to the output of the first inverter, the output of the second element And is connected to the third input of the start-stop unit, the second input of which is connected to the output of the main element OR, the second the input of which is connected to the input of the second inverter and to the output of the first memory unit, the fourth input of which is connected to the output of the address signal generation unit and to the fourth input of the second memory unit, the fifth input of which is connected with the fifth input of the first memory block, with the second output of the trigger and with the third input of the block of AND-OR elements, the first input of the trigger is connected to the first output of the code signal generation block and to the second input of the address signal generation block, the second trigger input is connected to the second output of the formation block code signals and to the third input of the address signal generation unit, the first input of which is connected to the output of the block of AND-OR elements, the first input of which is connected to the output of an additional OR element, the inputs of which are connected to third m, fourth, fifth forming unit outputs code signals and to the inputs of an encoder, which outputs a corresponding key to the first and second inputs of the second memory unit, moreover, the sixth output signal code generation unit connected to the respective inputs of the encoder.