SU788179A1 - Storage - Google Patents

Description

(54) DRIVE

The invention relates to measuring and computing techniques and is intended for use in digital measuring instruments and information processing systems. A device for accumulating and delaying digital information is known, which contains a trigger-shift register with which the delay Tj is adjusted. However, with a multi-bit information word and a large delay range, such a device becomes much more complex and cumbersome. By optimizing the structure of the circuit, it is possible to reduce the amount of equipment in this device by a known method 23. But even after optimization, the device will remain cumbersome, since its scheme is non-technological and does not allow the use of shift registers with one output. A closer technical solution to the invention is a device for accumulating information, containing a dynamic register, write and read amplifiers, erasers, a controlled oscillator, pulse counters, a generation failure trigger, augment. the start pulse datatapter, the end part decoder of the information part and the assembly circuit, the input of the controlled generator is connected to one of the trigger outputs, one of which is connected to the output of the assembly circuit and the other to the end part of the information section, the output of the controlled psdc generator to the input of the counter and one of the inputs of the expander, and the two inputs of the assembly are respectively connected to the output of the expander and to the button zgshisi, the output of the decoder of the starting pulse is connected to the driver via the assembly, and the input - with the output of the counter. The disadvantage of this device is the inability to control the magnitude of the accumulated information accumulator. The purpose of the invention is to expand the field of application of the accumulator of information on the shift registers, namely the implementation of a controlled delay of the accumulated information. The goal is achieved by the fact that in the accumulator containing shift registers connected to the information reading unit, a pulse generator, a trigger, an OR element, a pulse counter and an equivalence element, the first input of the OR element is connected to the control input of the reading unit, the second to the output of the pulse generator, the input of which is connected to the output of the trigger. The output of the OR element is connected to the clock inputs of the shift registers and the input of the pulse counter, the outputs of which are connected to one equipotential element input, the other corresponding inputs of which are information inputs of the device. The output of an element of equivalence is connected to the first input of a trigger, the second input of which is connected to one of the outputs of a pulse counter and one of the inputs of an element of equivalence.

Diagram of the device shown in the drawing.

The device contains an equivalence element 1 whose corresponding inputs are device information inputs, a pulse counter 2 connected by outputs to other inputs of an equivalence element 1, trigger 3, one input of which is connected to the output of an element of equivalence 1. the other - with the last output of the pulse counter 2, the generator 4. pulses, the input of which is connected to the output of trigger 3, element 5 OR, the second input of which is connected to the output of the generator of 4 pulses, block 6 shift registers, whose inputs are connected to the output of element 5 OR and the input of the pulse counter 2 and the readout unit 7, the control input of which is connected to the first input of the element 5 OR.

The device works as follows.

In the initial state, the counter 2 pulses and trigger 3 are reset and the generator of 4 pulses is turned off. Accumulated information is fed to the inputs of the block b shift registers. A code defining the number of ticks of accumulated information or the number of accumulated information words is applied to the corresponding information inputs of the equivalence element 1. At the first input of the element 5 OR and the control input of the block 7 of the read, external clock and 1 1Puls are received, identifying the accumulated: eMay information. From the output of element 5 OR pulses go to the clock inputs of the shift registers of block 6 and the input of counter 2 pulses. Each clock pulse shifts and records the information word into block b, in which information is accumulated (delayed). The number of clock pulses (the number of accumulated information words) is counted by a counter of 2 pulses, for you-j

The moves of which form a code equivalent to the number of received pulses (the number of accumulated information words). When the counter code arriving at the equivalence element 1 and the code defining the number of ticks of the accumulated information (the number of information words accumulated) become equal, the equivalence circuit 1 outputs a signal to the trigger 3, which triggers and turns on the generator of 4 pulses. The pulses of the generator 4, coming through the element 5 OR to the clock inputs of the shift registers of the block b and the input of the counter 2, shift the accumulated information to the output of the shift registers of the block b and summed in the counter 2 with the number of external clock pulses received by the time the generator 4 was turned on. Pulse frequency Generator 4. It must be such that during the pause between external clock pulses, the accumulated information can be advanced from the input to the output of the block shift registers b.

At the moment of accumulation of information at the output of the shift registers, the counter 2 pulses overflows and a pulse appears at its last output (the capacity of the counter is chosen to be numerically equal to the total information capacity of the accumulator). This pulse arrives at the other input of the trigger 3, which returns to its initial state and turns off the generator of 4 pulses. As a result, the counter 2 becomes zero, and at the output of the shift registers of the block b, accumulated information appears. With the arrival of the next clock pulse at the control input of the reading unit 7, the accumulated information appears at the output of the device.

The proposed device differs from the known possibility of controlling information delay, which expands the field of application of the device, it can be used both as a device for controlled clocked information delay, and as a storage device of adjustable information capacity.

Claims (3)

1. Kurochkin S. S. Multichannel counting systems and correlating 5. M., Energie, 1972, p. 265. 2. Smirnov N. I. and Zalichev N. N. The optimal structure of a tunable discrete delay line. - Instrumentation, 1977, № 1, p. 67. 3.The USSR author's certificate No. 243660, cl. G 11 C 21/00, 03/04/68 (prototype).