SU783793A1 - Device for stack addressing - Google Patents

Description

one

The invention relates to the field of computer technology and is intended for use in storage devices with stack organization included in the processor. five

A stack addressing device is known that contains one register of the stack position indicator {| 1. The disadvantage of such a device is the incomplete use of the volume of the stack memory or the excessive time spent on pumping and swapping the lower positions of the stack because of the initial value of the lower position of the stack fixed in equipment j (it is equal to zero).

Closest to the invention is a stack addressing device containing two registers of pointers storing the absolute addresses of the top and bottom positions of the stack area with reliable information, two comparison circuits for determining the 25 fill level of the stack memory M, analyzing the value of the register of pointers, and the scheme of fixing the moment of coincidence of the values of the pointers 30

Formula for calculating addresses and pointer values depending on the type of operation are summarized in a table.

The table uses the following notation: A is the absolute address of the beginning of the current stack position; DPS old value of the index of the top position of the stack; modified value of the index of the top position of the stack; OCR - the old value of the index of the lower position of the stack; The value of the index of the lower position of the stack; RPS - the size of the position of the stack.

The disadvantages of this device are that the field of application is limited only by memory: with word organization and in performance degradation when the processor is running with variable-length stack data. They arise from the fact that; the read and write operations and the stack data given are performed only over words of a fixed length, and the size of the stack position is unchanged and is set in hardware.

The purpose of the invention is to improve the performance of the device.

To achieve this goal, the stack addressing device containing the upper position pointer register, the lower position pointer register, the first and second control inputs of which are connected to the device's paging and pumping inputs, the output of the lower position pointer register is connected to the first input of the modification node entered address; adder, stack position modification unit, position number forming unit, stack position size register, the first and second correction nodes, receiving the data input of the first correction node is connected to the output of the modification node, and the data output of the first compensation node is with the pointer data input bottom position1 and stack. The first input of the adder is connected to the output register of the lower stack position indicator, the second input of the address adder is connected to the output of the Position Number Generation unit and the first data input of the stack position modification unit, and the output of the address adder is connected via the second correction node to the address output of the device. The output of the register of the pointer of the top position of the stack is connected to the first input of the data block of the formation of the position number and the second data input of the modification block: The positions of the stack, the data output of which is connected to the data input of the register of the pointer of the upper position of the stack. Input: generation dyes of the first and second correction nodes are connected to the device generation input, the data input of which is connected to the third data input of the stack position modification unit, the second data input of the position number generation unit and the input of the Sdannye register of the position size of the stack, the output of which is connected to the third the data input of the block forming the position number, the second input of the node modification and the fourth input of the block modifying the position of the stack. The read inputs of the stack position modification unit and the position number generation unit are connected to the device's read input, the rollout input input of the stack position modification unit is connected to the rollout input and device input, the offset input of the stack position modification unit is connected to the offset inputs of the position number and device generation unit, and the control the output of the modification unit with the control output of the device. The recording input of the block forming the position number is connected to the recording input of the device, the paging input of the block forming the position number is connected to the paging input of the device.

The block for forming the position number contains two OR elements, three AND elements, two subtractors, the first and second inputs of the first OR element are connected respectively to the read and write inputs of the block, the output of the first OR element to the first input of the first AND element, the second input of which is connected with the first data input of the block, and the output of the first element AND to the first input of the first subtractor, the first and second inputs of the second OR element are connected respectively to the inputs of the reading and paging unit, the output of the second OR element to the first input of the second th element and

the second input of which is connected to the third data input of the block, and the output of the second element And to the second input of the first subtractor, the output of which is connected to the first input of the second subtractor, the first and second inputs of the third element And are connected respectively to the second data input and the input of the offset of the block, and the output of the third element And - with the second input

the second subtractor, the output of which is connected to the output of the block.

The stack position modification unit contains an adder, two switches, an OR element and a number correction node, the first data input of the adder is connected to the second data input of the block, the second data input of the adder is connected to the output of the first switch, the first and second inputs of which are connected respectively to the third and fourth block data inputs. Controls input adder. connected to the output of the OR element, the first and second inputs of which are connected respectively to the reading and pumping inputs of the unit. The output of the adder is connected to the data output of the block and the first data input of the second switch, the second data input of which is connected to the first data input

the block, the control input of the second switch is connected to the offset input of the block, and the output is connected through the number correction unit to the control of the block output,

The first and second correction nodes contain a subtractor, an adder and a switch, with the input of the left operand of the adder connected to the input of the right operand of the subtractor, with the first.

the input of the switch and the data input of the correction node, the input of the left operand of the subtractor and the input of the right operand of the adder are connected to the input of the generation of the correction node, the output of the adder is connected to the data output

correction node.

Figure 1 shows the block diagram of the device stack addressing; FIG. 2 is a block diagram of a block of a position number; FIG. 3 is a block diagram of a modification block; Fig. 4 is a block diagram of a correction node.

The stack addressing device contains register 1 pointer of the lower position of the stack, register 2 pointer

top stack position, node 3 modifications, address adder 4, block

5 modifications of stack position, block

6 forming the position number, the stack position size register 7, the first correction node 8 and the second correction node 9.

Block 6 contains two .OR elements 10, 11, three elements AND 12, 13, 14, two subtractors 15, 16, read input 17, write output 18, first data input 19, paging input 20, third data input 21, second data input 22, offset input 23, output 24.

Block 5 contains an adder 25, two switches 26 and 27, an OR element 28 and a number correction unit 29, a second data input 30, a third 31 and a fourth 32 data inputs, a read input 33 of a pumping input 34, a data output 35, a first data input 36, bias input 37, control output 38.

The first and second correction nodes 8, 9 contain the subtractor 39, total 40, switch 41, data input 42, data output 43, generation input 44.

The operation of the stack addressing device when forming the address coming through the device’s address output to the stack memory unit consists of several successive stages: preparing the current position number, preparing the absolute address of the current position and modifying, if necessary, the values of the pointers of the lower and upper positions of the stack . This operation is controlled by a stack operation block that sends five control signals to the stack addressing device. Four of them correspond to the type of operation performed in the stack memory - signals Read

 Write, Paging, and Pumping, the fifth sets the version of the read or

output two operations I I

Read with write offset

or Record with offset

This is a reference to the pointer of the top position, reduced by a specified number of positions. The operation in this embodiment allows minimizing the number of actions for accessing the stack data that lies deep in the stack.

Signals Read, Write,

Pumping, Pumping

and

They are received through the control inputs of the device: the third, fifth, first, second, and fourth, respectively.

In the operations Read, Write, the address of the current position is calculated as the sum modulo M of the address from register 1 of the lower stack position index and the position number corrected by the type of operation that is referenced with respect to the index of the lower stack position. With swapping operations,

The rollback address is generated as an algebraic sum modulo M of the value from register 1 and the pointer correction value by type of operation. Correction of the pointer in all four operations is understood as taking into account the position of the pointer to the top or bottom position of the stack relative to the position to which it is being accessed: for example, the pointer to the top position of the stack is always set

It was added at the beginning of the next free position and for reading the last position it should be lowered by one position.

five

When modifying a value in register 2, the result is less than zero or more than the value of M, a control signal is generated and sent via the control output of the device to the stack operation unit about the presence of a value addressing outside the region with valid information.

The first stage of operation of the device is performed in block 6. Block 6 extracts the number of the current position, depending on the value in the index of the top position of the stack and the control

Reading

signals: at the signal.

the position number is (UVP - RPS), with the Record signal - UVP, with the Swap signal - RPS and with the Pumping signal, the value at the output of block 6 is zero.

Here-GWP - in the absence of a signal OFFSET; (UVP-SM) - in the presence of this signal;

OHR - value in the register 2 indexes of the top position, .stak;

RPS - the value in register 7 of the size of the position of the stack;

CM - the value of the input data from the processor.

Block 6 operates as follows. The first inputs of the subtractors 15, 16 and the adder 4 are the inputs for the decremented value, the second inputs for the subtracted value. At the first input of the subtractor 15 in the presence of at least one of the signals Read (input 17 of block 6) or i3a-:

The jumble (18 of block 6) at the inputs of the element OR 10 through the element 12 and passes the value from register 2, with the remaining operations, the value at the first input of the subtractor 15 is zero. If the input element OR 11 has at least one of the Read or Paging signals (input 20 of block 6) is passed to the second input of the subtractor, then the CRP value from register 7 is passed through the AND 13 element. For other operations, the value at the second input of the subtractor 15 will be

to zero. The output value of the subtractor 15 is the number of the current position at zero offset. The preparatory value of the current position number is fed to the first input of the subtractor 16, and to its second input through the element I 1 is supplied when defining a variant with a read in writing operations, the offset value (input 22 data from the processor) and subtracted from the preparatory value numbers, The result (numbers of the current position with regard to the offset) is fed through address output 24 to the second input of address adder 4. At the first input of address adder 4, register 1 of the lower position indicator of the stack, which contains the absolute address of the chronologically first record with reliable information, is permanently connected its number is zero. The output value of the address adder 4 is corrected modulo M by node 9 and is fed to the address output to the stack memory unit. The value in register 7 of the size of the stack position, which qualifies as a constant for modifying the values of the pointers and a constant for generating the absolute address of the current position, is set programmatically at the input from the processor. By changing the BIR value, you can dynamically change the format of the stack entries. The last stage of operation of the device is performed at node 3 and block 5; for read and write operations, the presence of a control signal Offset blocks the modification of the value in register 2, i.e. as a result of the implementation of this variant of these commands, the pointer of the top position of the stack remains with the same value. The modification of pointer values is performed simultaneously by node 3 and block 5, and depends on the values of the control signals from the block of stack operations. Node 3 modifies the value in register 1 of the lower position of the stack only during the Swapping and Pumping operations, and the value from the output of node 3 after modulo-M correction is recorded in node 8 in register 1 by the write control signal in the register. The correction modulo M, performed by node 8 (.or 9), is as follows:, check condition (or if the condition is not met, then algebraically sum the address value A and the modulus correction constant M equal to M, where the closest is greater to M, The sign is determined by the type of stack operation performed (in particular, for the second correction node 9, Read and Write specify the addition of the UNP and the correction constants), and Swap - subtract the constant from the UNP with subsequent discarding of the possible transfer from the older (nth) bit yes, i.e., the UNP M is performed on The bottom of the adder. Nodes 8 and 9 are of the same type in structure. The inputs of the left operand of the subtractor 39 and the input of the right operand of the sump 40 are permanently connected to the device generation input, which is the output of the constant value generating node of 2 N. Control inputs that determine the type of actions on adder 40 (addition and subtraction) are not shown in Figure 4. A signal is generated at the output of the subtractor 39, indicating whether the condition A7 M is fulfilled for node 8 (or UNP7 for M. 9). If this signal is missing, then the output 43 of the data comes through the switch 41 value from the input 42 of the data. Otherwise, and if there is a control signal generated by the type of operation in accordance with the table, the output 43 of the data receives the value from the output of the adder 40. In this case, when the operation is performed, it does not require correction (at the node B address or at node 9 the value of the SNP) to the output 43 of the data is supplied with the input value from the input 42 of the data. In block 5, two actions are performed; generating the number of the first free position of the stack for entering into the register 2 of the index of the top position of the stack and checking whether the number of the current position does not exceed the value of M, the first action is performed in accordance with the values of the control signals at the input of the device (see table), the second action is to check whether the ratio O NP M is satisfied, (1) where the NP position number or the result of performing the first action in block 5 with no control Signal Offset, or the value from the output of block b in the presence of the specified signal. The entry of a value into a register 2 is performed in the absence of a signal. The 3an5i shift of the signal into the register (this signal is not shown in Fig. 1). Block 5 when modifying the position number works as follows (fig.Z). The value of register 2, i.e. The CIP is supplied via the second input 30 of the block to the first input of the adder 25, the second input of which is connected to the switch 26, which selects either the PSD from the input 32 of the block or the value from the input 31 of data from the processor as a modification constant; the control input of the adder 25 is connected to the OR element 28, which combines the control signals Read (input 33 blocks) and Pumping (input 34 blocks), the presence of one of them sets the subtraction on the adder 25, the absence of both - addition. The output of the adder 25 is connected at the output 35 of the block to the input of the register 2 and through the second switch 27, to the second input of which the value comes from the block b through the input 36 of the block, to the number correction unit 29.

The node 29 converts the output value of the switch 27 to the value modulo M, the appearance of the transfer at the output of the switch 27 indicates the presence of an overflow or disappearance of the stack. Selection

neither

one of the input values by the switch 27 is set by the control signal coming through the input 37 of the offset of the block. If there is, the input from the switch 27 gets the value from the input 36 of the block. The control signal for selection in switch 26 is not shown.

Thus, when setting, for example,. Recording operations and a variant without offset, the adder 25 sums up the value of the PSD with the CWP value, generates a new value at output 35 for writing to register 2, and the result via switch 27 hits the correction node 29 that checks condition (1).

It is possible to perform in block 5 a modification of the value of the pointer of the top position of the stack with the value specified by the program, for example, from

processor, at input 31. In this case, the register 2 (output 35) is sent the value

Jurt-vun CH.

The sign of the operation, addition or subtraction is specified by the control signals at the inputs of the reading and pumping 33, 34 of the modification block. For example, the presence of a signal Reading from a stack operation block causes a decrease in the value of the pointer, i.e. UVP-UVP-SM. Checking the condition (1) for the new CWP value is performed by the correction unit 29, to the input of which the control signal Offset (input 37 of block 5) switches the value 27 via the switch 27

5 UVP from the output of the adder 25.

The use of this stack addressing device expands the scope of stack storage — you can;: equally effective, use

0 as a stack memory block is not only a memory with a complex organization, but also a byte memory, which is the most common at the present time, while the memory size is not limited to values equal to 2.

five

The application of the proposed device ensures the complete use of the entire volume of the stack memory both when and when it allows the placement in the stack memory of

0 or more stack positions compared to a known device. This is equivalent to an increase in the volume of the stack memory and, consequently, an increase in the performance of the processor due to the significant difference (4-10 times) in the speed of the stack and main memory.

Claims (3)

Reading (UNP + UVP RPS) t "1M UVP-RPS Record - (UNP + UVP: p M UVP + RPM Swapping (UNP-RPS1 about {M UVP + RPS Pumping UNP UVP-RPS The formula of the invention 1. The stack addressing device containing register pointer upper position of the stack, register pointer bottom 65 UNP (UNP-RPS) adoo1 (UNP + RPS) “on it is the stack position, the first and second control inputs of which are connected respectively to the paging and pumping inputs of the device, the register output of the lower-position pointer is connected to the first input of the modification node that is different that, in order to improve the performance of the device, an address adder, a stack position modification unit, a position number generating unit, a stack position size register, the first and second correction nodes are entered, the data input of the first correction node is connected to the output uyla modifications, and the data output of the first correction node with the register data entry of the lower position indicator of the stem, the first input of the address adder is connected to the register output of the lower position indicator of the stack, the second input of the address accumulator - with the output of the position number generation unit and the first data input of the position modification block the output of the address adder is connected via the second correction node to the address output of the device, the register output of the top position of the stack is connected to the first data input of the unit The position window and the second data input of the stack position modification block, whose data output is connected to the data register of the upper position indicator, the generation inputs of the first and second correction nodes are connected to the device generation input, whose data input is connected to the third data input of the stack position modification block , the second data input of the block of forming the position number and the data input of the register of the position size of the stack whose output is connected to the third inlet of the data of the block of forming the position number, the second input of the mod node and the fourth data input of the stack position modification block, the inputs of the stack position modification block and the position number generation block are connected to the read input of the device the rollout input of the stack position modification block is connected to the rollout input of the device, the offset input of the stack position modify block is connected to the offset inputs the fop of the position number and device, and the control output of the modification block is controlled by the device output, the recording input of the position number forming unit is connected to the recording input device, the paging input of the block forming the position number is connected to the paging input of the device. 2. The device according to claim 1, about tl and the fact that the unit for forming the position number contains two elements OR, three elements AND, two subtractors, the first and second inputs of the first element OR are connected respectively to the read and write inputs of the block, the output of the first element OR is the first input of the first element I, the second input of which is connected to the first data input of the block, and the output of the first element I to the first input of the first selector, the first and second inputs of the second element OR are connected respectively to the read and swap inputs block output wto element OR - with the first input of the second element AND, the second input of which is connected to the third data input of the block, and the output of the second element AND - about the second input of the first header, the output of which is connected to the first input of the second subtractor, the first and second inputs of the third element AND connected, respectively, with the second data input and the input offset of the block, and the output of the third element I - with the second input of the second subtractor, the output of which is connected to the output of the block, 3. The device according to claim 1, that is, that the block for modifying the stack position contains a summator, two switches, an OR element and a number correction node, the first data input of the adder is connected to the top data input of the block, the second input data summer - with the output of the first switch, the first and second inputs of which are connected to the third and quarter inputs of the block, the control input of the adder is connected to the tricks of the OR element, the first and second inputs of which are connected to the input and output of the block, respectively, the output sum The controller is connected to the data output of the block and the first data input of the second switch, the second data input of which is connected to the first data input of the block, the control input of the second switch to the offset input of the block, and the output of the second switch is connected to the control output of the block . 4, The device according to claim 1, that is, that the first and second correction nodes contain a subtractor, a cyrvSMaTop and cog-1 switch, with the input of the left operand of the adder connected to the input of the right operand of the subtractor, the first input of the switch and the data of the node correction, the input of the left operand of the subtractor and the input of the right operand of the summatf are connected to the input of the generation of the correction node, the output of cyNMaTOpa is connected to the second input of COMiviyTa.TOpa, the output of which is connected to the output 4 of the data of the correction node. Sources of information taken into account in the examination of the invention 1.US Patent 3,200,379, cl. 340-172.5, 1965. 2, US Patent If 3810117, cl. 340-172,5, 1974 (prototype). Put.Z 18VGGG019