JP3517579B2 - Microprocessor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for reading and executing an instruction from a memory in which the instruction is stored.

[0002]

2. Description of the Related Art With the recent development of LSI technology, the capacity of memory has been increasing, and along with it, a new type of microprocessor capable of handling a wide address space has been developed. At the time of this development, an old microprocessor that can only handle a narrow address space is used as a base, and a new register for the upper digit of address data representing a wide address space is newly provided to expand the narrow address space. Is generally done.

FIG. 1 is a diagram showing an example of a register set (A) provided in an old microprocessor and a register set (B) provided in a new microprocessor. The old microprocessor includes a program counter 11, a general-purpose DE register 12, and a general-purpose H.
Registers such as the L register 13 and the stack pointer 14 are provided. Each of these registers has a bit width of 16 bits, and the addresses that this old microprocessor can handle are addresses from 0000h to FFFFh in hexadecimal notation. Below, the number with the last "h" is 16
It is assumed to be in decimal notation.

Even newer microprocessors have a program counter 1 with a bit width of 16 bits each.
5, a general-purpose DE register 16, a general-purpose HL register 17, and a stack pointer 18, and a PPC register 19 each having a bit width of 8 bits,
A ZP register 20 and an XP register 21 are provided. PPC register 19 and program counter 1
5 is used as one register in which both are combined. In addition, ZP register 20 and XP register 2
Any one of 1 is selected and used in combination with the general-purpose DE register 16, the general-purpose HL register 17, and the stack pointer 18, respectively. As a result, the new microprocessor can handle addresses from address 000000h to FFFFFFh. Considering the address space that the old microprocessor can handle as one page, the new microprocessor can handle it. The address space that can be used is an address space for 256 pages. In the following, the address space and memory will be described as having such pages. The ZP register 20 and the like are used as a page register that stores data indicating a page included in the address space and the memory.

[0005]

By the way, there is a large accumulation of software created for old microprocessors, so that new microprocessors with expanded address spaces can use these software as they are. It is desirable that the microprocessor be capable of so-called compatibility. In order for the new microprocessor to have such compatibility, the instruction notation used on the old microprocessor such as the assembler language character string and the machine instruction code remains unchanged on the new microprocessor. The instruction contents that are used and executed according to their instruction notation on the newer microprocessor must be consistent with the instruction contents that are executed according to those instruction notation on the older microprocessor Is.

Conventionally, as a new type of microprocessor having such compatibility, the instruction notation and instruction contents used in the old type microprocessor are used as they are, and the data stored in the page register is directly specified. There is known a first microprocessor that is newly prepared with an instruction notation and instruction content for executing. In this microprocessor, for example, a character string "LD ZP, A" and an instruction code corresponding to the character string are prepared as a new instruction notation, and the instruction notation is the same as "the data stored in the accumulator. The data is stored in the ZP register. "

However, a machine language instruction code prepared as such a new instruction notation has a long byte because an instruction code having a short byte has been almost used as an instruction notation for an old microprocessor. The instruction code has a length. As a result, there is a problem in that the size of a program in machine language tends to be large and the effective speed tends to be low. Within the program,
The page is often specified by using the operation result, but in this case, this problem becomes particularly noticeable because the frequency of use of the instruction code having a long byte length increases. Further, this first microprocessor has a problem that the number of new instruction codes prepared is large and the circuit for decoding the instruction code becomes large.

As the new microprocessor, the instruction notation used on the old microprocessor is used as it is, and the internal state is maintained before and after the execution of the instruction in the old microprocessor such as "LD A, A". The instruction notation used as the instruction notation indicating the meaningless instruction is an instruction indicating a significant instruction such as “using the data stored in the ZP register as data designating an accessible page”. A second microprocessor used as a notation is also known.

However, in the second microprocessor, when a program created for an old microprocessor is used as a subroutine, it was expected that it would be executed as a meaningless instruction when the program was created. There is a problem that an instruction may be executed as a significant instruction and an abnormal operation may occur. In view of the above circumstances, an object of the present invention is to provide a microprocessor that has a wide address space in which the address space of the old-type microprocessor is expanded and that software for the old-type microprocessor can be used as it is.

[0010]

According to another aspect of the present invention, there is provided a microprocessor for reading out instructions from a memory in which a plurality of instructions are stored and executing the instructions, in which data representing a page of the memory is stored. One or more page registers provided corresponding to each predetermined instruction, and an accumulator in which a predetermined instruction different from each predetermined instruction associated with the page register is associated; Either one of the above page register and accumulator is selected, and the data stored in the selected page register or the entire or partial area of the selected accumulator having the same bit width as the page register bit width The data stored in is stored in the data that specifies the accessible page of the above memory. And page designation circuit to output as,
An instruction interpretation unit that interprets an instruction to be executed,
When the instruction interpreting unit interprets the instruction interpreted by the instruction interpreting unit as one of the one or more page registers or the instruction associated with the accumulator, the instruction interpreting unit notifies the page designating circuit of the interpreted instruction. It is characterized in that the page register or accumulator associated therewith is selected.

The microprocessor of the present invention comprises a judgment circuit for judging whether or not the address of the memory in which the instruction to be executed is stored is an address within a predetermined area. If the determination circuit determines that the address is outside the predetermined area and the instruction interpreted by the instruction interpreter is an instruction associated with the accumulator, the accumulator is selected in the page designation circuit. It is desirable that it be something that can be done.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 2 is a diagram showing an embodiment of the microprocessor of the present invention. This microprocessor 100
Is an external bus 112 in a memory 110 in which instructions are stored.
This memory 110 is connected to the memory 110, and the memory 110 includes a compatible area 111 of 2 16-bits from address 000000h to address 00FFFFh in which a program created for an old microprocessor is stored.
It has an address space of raised bits.

Further, the microprocessor 10 shown in FIG.
0 includes a program counter 121, a general-purpose DE register 122, and a general-purpose H each having a bit width of 16 bits.
An L register 123 and a stack pointer 124 are provided, and data is stored in these registers via the bus 130 and is taken out from these registers. The microprocessor 100 also includes an accumulator 125 and a PPC each having a bit width of 8 bits.
A register 126, a ZP register 127, and an XP register 128 are provided, and the data in these registers are also stored and retrieved via the bus 130. The PPC register 126 is a register used together with the program counter 121, and stores data indicating a page of the memory 110 in which an instruction to be executed is stored. The ZP register 127 is a general-purpose DE register 12
2, general-purpose HL register 123 and stack pointer 1
24 is a page register used together with each, and stores data indicating a page of the memory 110.
The XP register 128 is a page register similar to the ZP register 127.

The microprocessor 100 is also provided with an instruction interpretation execution circuit 140 and an access circuit 170, which are stored in the PPC register 126 and the program counter 121 of the memory 110 by the instruction interpretation execution circuit 140. The instruction stored at the address indicated by the stored data is read via the access circuit 170 and the external bus 112, the read instruction is interpreted and executed, and the memory 1 via the external bus 112 or the like is read.
10 is accessed, and various data is stored / retrieved / calculated via the bus 130. This instruction interpretation execution circuit 14
The instruction notations that 0 can interpret are the instruction notations used in older microprocessors, and these instruction notations correspond to instruction codes that have a short byte length. Further, the ZP register 127 is associated with the instruction represented by the instruction notation “LD D, D”, and the XP register 128 is associated with the instruction represented by the instruction notation “LD E, E”. They are associated with each other, and the accumulator 125 is associated with the instruction represented by the instruction notation “LD A, A”. When an instruction represented by an instruction notation such as "LD D, D" is executed in the instruction interpretation and execution circuit 140, a signal indicating a page register or an accumulator associated with the instruction is generated.

Further, the microprocessor 100 is provided with a judging circuit 150, and the judging circuit 150 is provided.
It is determined whether or not the value of the data stored in the PPC register 126 is "00h", and the address where the instruction read by the instruction interpretation and execution circuit 140 from the memory 110 is stored in the compatible area. It is determined whether the address is within the address. This determination result is input to the instruction interpretation execution circuit 140.

Further, the microprocessor 100 is provided with a multiplexer 160 corresponding to the page designating circuit according to the present invention.
In the case of 0, the page register or accumulator generated by the instruction interpretation execution circuit 140 when the determination circuit 150 determines that the address where the instruction read from the memory 110 is stored is outside the compatible area. Is input. Further, a ZP register 127, an XP register 128 and an accumulator 125 are connected to the multiplexer 160, and the multiplexer 160 includes an instruction interpretation execution circuit 140.
According to the signal generated by the ZP register 12
7. Any one of the XP register 128 and the accumulator 125 is selected, and the data stored in the selected page register or accumulator is transferred to the upper side of the address line of the memory 110 via the access circuit 170 and the external bus 112. Output for 8 bits. As a result, a page of the memory 110 that can be accessed by the instruction interpretation and execution circuit 140 is designated.

FIG. 3 is a diagram showing how an instruction is executed in this embodiment. FIG. 3 shows the address space of the memory 110 shown in FIG. 2. As described above, the compatible area 111 is from address 000000h to address 00FFFFh. A subroutine program “_SUB” created for an old microprocessor is stored in the compatible area 111, and a newly created subroutine program “_SUB” is used in the address space excluding the compatible area 111. The stored program is stored. The instruction notation of each instruction that constitutes these programs is all the instruction notation used in the old-type microprocessor, and the instruction code corresponding to these instruction notation is an instruction code having a short byte length. is there.

Execution starts from an instruction 201 represented by the notation "LD D, D", and since this instruction 201 is stored outside the compatible area 111, the ZP register is selected by the multiplexer 160 shown in FIG. To be done. Next, the instruction 2 represented by the notation "LD ZP, 01h"
When 02 is executed and the value “01h” is stored in the ZP register, the value “01h” is output to the upper 8 bits of the address line of the memory 110 shown in FIG. 2 and the value “01h” is output.
The page indicated by “h” is designated as an accessible page.

Next, the instruction 203 represented by the notation "LD HL, 8000h" is executed, the value "8000h" is stored in the general-purpose HL register, and "CALL--SU".
The instruction 204 represented by the notation “B” is executed, the flow of the program moves to the subroutine program “_SUB” stored in the compatible area 111, and “LD
The instruction 205 represented by the notation “A, A” is executed.
Since this instruction 205 is stored in the compatible area 111, the instruction 205 is executed as a meaningless instruction, and the selection of the ZP register and the page designation by the multiplexer 160 shown in FIG. 2 are maintained.

Thereafter, the instruction 206 represented by "RET" is executed and the flow of the program returns,
The instruction 207 represented by the notation “JP (HL)” is executed. The page specified by executing the instruction 201 and the instruction 202 is maintained after the execution of the subroutine, and when the instruction 207 is executed, the page indicated by the value stored in the ZP register and the general-purpose HL register is indicated by 018.
The program flow jumps to address 000. As described above, according to the microprocessor of the present embodiment, it is possible to effectively use the program created for the old microprocessor as a subroutine.

Next, the instruction 208 represented by the notation "LD DE, F000h" is executed to store the value "F000h" in the general-purpose DE register, and "ADD HL, D".
The instruction 209 represented by the notation "E" is executed, and the value "8000h" stored in the general-purpose HL register is added to the value "F000h" stored in the general-purpose DE register to show the calculation result. The value "7000h" is general-purpose HL
Stored in register. Next, the instruction 210 represented by the notation “ADC A, 10h” is executed, and the instruction 209 is executed.
The value "11h" obtained by adding the carry generated by and the value "10h" is stored in the accumulator.

Next, "L" which is the same as the instruction notation of the instruction 205
The instruction 211 represented by the notation “DA, A” is executed. Since this instruction 211 is stored outside the compatible area 111, the multiplexer 160 shown in FIG.
The accumulator is selected, and the value “11h” stored in the accumulator is output to the upper 8 bits of the address line of the memory 110. Next, the instruction 2 represented by the notation “JP (HL)” which is the same as the instruction notation of the instruction 207.
12 is executed, and since the page is designated by the value “11h” stored in the accumulator, the program flow jumps to the address 117000h. As described above, according to the microprocessor of the present embodiment, even when a page is designated by using the operation result, the page can be designated only by the instruction code having the short byte length.

The compatible area in this embodiment is 00.
Although it is an area from address 0000h to address 00FFFFh, the predetermined area in the present invention may be another area in the address space. Further, in the present embodiment, the page register or accumulator is selected by the multiplexer.
The register may be selected from a register group including an H register and an L register.

Further, in the present embodiment, the bit width of the accumulator and the page register are the same, but the accumulator according to the present invention has a bit width larger than that of the page register. In this case, the data stored in a partial area of the accumulator is used as the data designating the page.

[0025]

As described above, the microprocessor of the present invention has a wide address space in which the address space of the old-type microprocessor is expanded. According to the microprocessor of the present invention, the old-type microprocessor is provided. The software for the processor can be used as it is.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a register set (A) provided in an old microprocessor and a register set (B) provided in a new microprocessor.

FIG. 2 is a diagram showing an embodiment of a microprocessor of the present invention.

FIG. 3 is a diagram showing how an instruction is executed in this embodiment.

[Explanation of symbols]

100 microprocessor 110 memory 111 compatible area 125 accumulator 126 PPC register 127 ZP register 128 XP register 140 instruction interpretation execution circuit 150 judgment circuit 160 multiplexer

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-61-290549 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/30-9/36 G06F 9 / 40-9/42

Claims (2)

(57) [Claims] 1. A microprocessor for reading and executing an instruction from a memory in which a plurality of instructions are stored, and one or more provided corresponding to each predetermined instruction, in which data representing a page of the memory is stored. Of the page register, an accumulator in which a predetermined instruction different from each of the predetermined instructions associated with the page register is associated, and any one of the one or more page registers and the accumulator The data stored in the selected and selected page register or the data stored in the entire area or a partial area of the selected accumulator having the same bit width as that of the page register is accessed in the memory. A page design circuit that outputs as possible page designating data and an attempt to execute An instruction interpreting unit that interprets an instruction, wherein the instruction interpreting unit is an instruction associated with the accumulator, and the instruction interpreted by the instruction interpreting unit is one of the one or more page registers. A microprocessor characterized by causing the page designation circuit to select a page register or an accumulator associated with the instruction. 2. A determination circuit for determining whether or not an address of the memory in which an instruction to be executed is stored is an address within a predetermined area, wherein the instruction interpretation unit is configured to operate by the determination circuit. The page designating circuit selects an accumulator when it is determined that the address is outside the predetermined area and the instruction interpreted by the instruction interpreting unit is an instruction associated with the accumulator. The microprocessor according to claim 1, wherein: