SU769733A1 - Pulse-phase code-to-voltage converter - Google Patents

Description

one

The invention relates to an analog-digital computing, as well as a measurement technique, namely, a technique for transforming information, and can be used in various devices operating in a phase-pulse code with any base.

A device for converting a code into a voltage is known by intermediately converting a code into a time interval and averaging the latter, comprising a code converting unit into a time interval whose output is connected to the control input of the key, the second input of which is connected to the reference voltage source, and the output of the key is connected to input output averaging device 1.

However, this device has a low speed.

Another converter is known, which is the closest to the technical essence and the achieved result to the invention, in which the parallel conversion of code bits in time intervals is carried out, the latter are averaged, and the output voltages of averaging devices are summed. This converter contains blocks (chronotrons) for storing and converting a phase-pulse code into an emitting-pulse code, the inputs of which are connected to the output of the clock generator, averaging blocks (integrators) and electronic switches, the first five inputs of which are connected to the source of the reference voltage, and the outputs the inputs of the averaging devices 2. The disadvantage of this device is its closeness, since it uses

10 a large number of analog elements (n keys, n integrators and n weight resistors), therefore as a result of the non-ideality of the parameters of the used analog elements and the spread of these parameters

15 The conversion accuracy and stability of the device parameters are low.

The aim of the invention is to increase the conversion accuracy and stability of the converter parameters.

20 This is achieved by converting the phase pulse code to voltage converter, which contains a unit for storing and converting the phase pulse code into a pulse width, for example,

25 of the l-bit register and n R-S-flip-flops, the S-inputs of which are respectively connected to the outputs of the register, the clock input of the latter is connected to the output of the clock generator, averaging

30 block and key, the first input of which is connected to the source of the voltage, and the output - to the input of the averaging unit, n frequency dividers, l-qaial level distributor, (-1) D-flip-flops, two elements of the AND and the element ILR1 , all frequency dividers and an r-channel level distributor are connected in series, the output of the clock generator is connected to the input of the frequency divider, the output of which is connected to the R-input of the RS-trngger of the first bit on the C-inputs of D-flip-flops, the outputs of the subsequent dividers are connected to Respectively with the R-inputs of the RS-triggers junior bits and D-inputs of D-flip-flops, the outputs of which are respectively connected to the first inputs of the elements And the first group, the second inputs of the latter are connected to the outputs of the corresponding RS-Tringers of the lower bits, the output of the RS-trigger high the bits and outputs of the elements of the first group are connected respectively to the first inputs of the elements of the second group, the second inputs of which are connected to the corresponding outputs of the n-channel level distributor, and c) the inputs of the elements of the second group are connected to the inputs of the OR element, the output of which is connected to the second input of the key.

FIG. 1 represents the plow circuit of the device on a three-bit converter; in fig. 2 - voltage diagrams for the operation of the device.

The phase-momentum code (in particular, decimal) to voltage converter contains a block 1 for storing and converting a phase-mimic code into a latitude pulse code consisting of a three-bit register 2 and RS-flip-flops 3, 4 and 5, the S-inputs of which are connected to register outputs. The clock input of the latter is connected to the generator output of 6 clock pulses. In addition, the converter contains an averaging unit 7 (naimer, integrator) and a key 8, the first input of which is connected to the source of reference design 9, and the output to the averaging unit 7.

Three frequency dividers 10, 11 and 12 and a three-channel level distributor 13, two D-trnggers 14 and 15, the first group of elements AND 16 and 17, the second group of elements AND 18, 19 and 20, as well as the element OR 21 are entered into the converter. All frequency dividers 10, And and 12, and a three-channel level distributor 13 are connected in series. The output of the generator 6 is connected to the input of the first frequency divider 10, the output of which is connected to the R-input of the RS flip-flop 3 of the highest bit and to the C-inputs of the D-flip-flops 14 and 15. The outputs of the subsequent dividers And 12 are connected respectively to the R-inputs of RS - triggers 4 and 5 low-order bits on the D-inputs of D-flip-flops 14 p 15. The outputs of the subsequent respectively are connected to the first inputs of the elements And the first group 16 and 17, the second inputs of which are connected to the outputs of the corresponding RS-triggers 4 n 5 lower bits . Output RS-flip-flop 3 senior bits and outputs of the elements And nerve groups 16 and 17 are connected respectively to the first inputs of the elements And the second soil 18, 19 and 20, the second inputs of which are connected to the corresponding outputs of the three-channel distributor of levels 13. The outputs of the elements And the second group 18 , 19 and 20 are connected to the corresponding inputs of the OR element 21, the output of which is connected to the second control input of the key 8.

The Converter operates as follows.

The generator 6 generates a sequence of pulses a (see Fig. 2) with a frequency / t, which are fed to a three-bit register 2 and the first divider 10, from which output the reference emulsions Ci with a frequency fo fT / IO are fed to the R input of the trigger 3, the S-input of which receives the pulses fei from the output of the high bit of register 2. RS-flip-flop 3 generates pulse-width sequences / whose pulse duration is proportional to the recorded digit in the high bit of register 2, since the phase shift of the emulses bi relative to the pulses of the reference sequence the frequency Ci with frequency / o is determined by the digit of the highest bit of register 2. From the outputs of the least significant bits of the latter, the S-inputs of the RS flip-flops 4 and 5 receive pulses bz and b, the R-inputs of which are given emulsions Ca and Cz with frequencies / 0/10; о / ЮО from the outputs of dividers PI 12. R-S-flip-flops 4 and 5 form sequences / 2 and 3, the pulse durations of which are proportional to the additional code of digits of the least significant bits.

These sequences are fed to the second inputs of the AND elements of the first group 16 and 17, to the first inputs of which polarization pulses p and pz are applied. The latter are formed by the corresponding

D-trngger 14 and 15, on the clock C-inputs of which the reference pulses Cc a arrive; the D-inputs are the pulses Ca and C3 from the outputs of the corresponding frequency dividers 11 and 12. Elements of the first group 16 and 17

form pulse-width sequences TI and G2 with frequencies / o / o and / 0/100, the duration of the pulses of which is proportional to the direct code of the numbers recorded in the lower bits of register 2.

Pulse width sequences / 1 from the output of the R-S flip-flop 3 and Gj rz from the outputs of the elements 16 and 17 are fed to the first inputs of the corresponding elements of the second group 18, 19 and 20, to the second inputs

which do not overlap

strobe pulses mi, t, gpz (the duration of which is equal to or a multiple of the duration of the pulses of the least significant bit) from the corresponding outputs of the three-channel level distributor 13, ensuring alternate passage of the latitudinal mp3 sequences through the AND elements of the second group 18, 19 and 20. From the outputs of the latter to the inputs of the element OR 21, the non-overlapping Sb S2, 83 pulse-width-distributed sequences arrive. The element OR 21 forms a single intermediate sequence of pulses Wj whose period is equal to the sums Periods of non-overlapping pulse-width sequences Sj, S2, 53. The pulses W arrive at the control input of the key 8 by connecting the source of the reference voltage 9 to the integrator 7 for the duration of each pulse.

The output voltage of the integrator is analogous to the original number recorded in the register.

In such a converter, the accuracy and stability of the parameters is improved by eliminating the weight resistors and reducing the number of analog elements - switches and integrators.

Reducing the number of used analog elements not only reduces the error of conversion and increases the stability of parameters, but also increases the reliability of the device as a whole.

Claims (2)

1. Klebansky, R. B. Code-to-Objective Converters. - M .: Energie, 1973, p.31, rice 1-14. 2. USSR author's certificate number 163437, cl. H OZK 13/14, 22.06.60 (prototype).