SU765784A1 - Device for testing logic units - Google Patents

Description

one

The invention relates to changes and controls and can be used to visually monitor the parameters of logical blocks.

Devices are known for controlling 5 logic blocks, comprising a control board, rectifier, diode bridge, indicators, amplifier, selectors and synchronizers 1. and 2 .

The disadvantage of these devices is that the information content is small and the application area is narrow.

The closest in technical essence to the present invention is the device | 3, adopted for the proto-15 type and containing the first and second comparators, whose inputs are connected respectively to the first and second inputs of the device, the first and second triggers, the output of the first trigger is-20 to the first inputs of the first key and the comparison unit, the output of the second trigger to the first input of the second key and the second input of the comparison unit, the outputs of the first and second keys 25 are connected via the corresponding shift registers to the first and second inputs of the switch torus, connected respectively to the second inputs of the first and second keys, the third input is com-30

the mutator is connected to the T1 network of its trigger, the first input of which is connected to the first output of the pulse distributor, the second input to the first input of the fourth trigger and the second output of the pulse distributor connected to the first input to the output of the first frequency divider, the second input to the first input of the first frequency divider and to the output of the comparison unit, the third input to the third device input to it, the second input of the first frequency divider is connected to the first inputs of the first and second triggers, the second inputs of the shift registers and output ode pulse maker connected by the first input through the third key to the output of the second frequency divider, whose input is connected to the output of the pulse generator, the output of the fourth trigger is connected to the second input of the third key and the third inputs of the first and second keys, the second input is connected to the fourth input of the device and with the third input of the comparison unit, the fourth input of which is connected to the fifth input of the device, the second input of the pulse former and the second input of the second frequency divider are connected respectively to the sixth and a seventh input device.

A disadvantage of this device is its limited functionality.

The aim of the invention is to expand the functionality of the device.

This is achieved by introducing a counter, adder, step voltage generator, as well as the first and second logic blocks, the first inputs of which are connected to the outputs of the first and second comparators, respectively, the second inputs - to the eighth input of the device, and the outputs - to the second the inputs of the first and second triggers, respectively, the input of the counter is connected to the second output of the pulse distributor / and you go, to the fourth input of the switch and via the step voltage generator to the first input of the adder connected second m input to the output switch.

The drawing shows a block diagram of the device, which shows the first and second comparators 1 and 2, the first and second logic blocks 3 and 4, the first and second triggers 5 and b, the first and second keys 7 and 8, the first and second shift registers 9 and 10, switch 11, adder 12, step voltage generator 13, counter 14, comparison unit 15, pulse generator 16, first frequency divider 17, third switch 18, pulse generator 19, second frequency divider 20, pulse distributor 21, third and fourth triggers 22 and 23 g inputs 24-29, output 30, inputs 31, 32 and you 33 od the device.

The device works as follows, j

The device is constantly in one of two modes, in the recording mode, or in the information reading mode. In both modes from the output of the generator 16 to the input of the divider 20 pulses of the reference frequency. The divider 20 has two outputs, on the first of which constant frequency pulses are formed, which are necessary for reading information, and on the second one, pulses with a frequency determined. the division factor set by the signals from the device input 27, necessary for recording information.

The device is in recording mode.

A start signal is applied to input 24, which triggers 23 to its initial state, and through block 15 - divider 20 and distributor 21,

The information from inputs 31 and 32 is fed to the inputs of input comparators 1 and 2, which quantize signals with respect to the three voltage levels set for the selected series of logic elements of the input voltage

switching, maximum logic voltage O and minimum logic voltage 1.

Depending on the value of the signal from input 28 to the inputs of blocks 3 and 4, there are two possible quantization modes.

In the first mode, the siPal is quantized with respect to the input voltage

0 switching, directly fed to the input 3 of the trigger 5 or 6. In the second mode, the signal at the inputs 5 - triggers 5 and b is determined by the formula:

 - SoASjV S,.

where 0 1 ;; if the input signal exceeds the maximum logic level O, S, 1, if the input signal exceeds the minimum logic level 1, $ 2 - output signal

 trigger

In both quantization modes, the signal at the input K of the flip-flops 5 and b is obtained by inverting the signal at the input O. The second quantization mode is necessary for diffusion; Three-level signals or broken wires without increasing the capacity of the shift registers.

Writing information to triggers 5

0 or b is effected by a clock pulse received from the output of the former 19.

Depending on the control signal arriving at the input of driver 19 from input 26, the clock pulses may have the following form: the duration of the sync pulse is much less than its period.

In this case, the trigger 5 or b takes the state defined by the value Sj at the moment of arrival of the pulse, which corresponds to the synchronous recording of information. The difference between the follow-up period and the duration of the clock pulses is significantly less than the period

5 the duty cycle is a- 1 /. At the same time, the trigger 5 or b saves its state, if the clock period Sj has not changed and changes to the opposite, if $ 3 has changed by time,

0 is enough to trigger trigger 5 or b. This allows the fixation of pulses, the duration of which is significantly, less than the quantization period,

From the output of the flip-flops 5 and b, the information is fed to the input of the registers 9 and 10 on the bits and written to them, but not read. The transition from the write mode to the read mode is performed by block 15,

0 depending on the signal at input 24, it is possible to switch to the read mode at the end of the trigger signal at input 24, or at the time of matching the input signals with the code received at input 25 of the building ,;

In the first (5th ray, the impulse from input 24 passes unchanged to the output of block 15.

In the second case, the leading edge of the signal from input 24 causes the formation of a logical O at the output of block 15.

Switching to the logical 1 state occurs at the moment when the output of the triggers 5 and b to the inputs of the block 15 enters in the parallel Code information that coincides with the code

The input from input 25. In both cases, the nepexoji of the output signal of the block1 15 from the state of the logical exhaust gas to 1 will trigger the divider 20 on n and the distributor 21 for m bits. Through the number of ticks equal to the product of p and the difference m and the delay determined by the signal from input 29, a second pulse is generated at the second output of the distributor 21, which triggers the triggers 22 and 23 to the local state 1. The signal coming from the output of the trigger 23 switches the keys 7 , 8 and 18 are in the state corresponding to the read mode.

The operation of the device in read mode.

Registers 9 and 10 through the keys 7 and 8 are closed in a ring and the information circulates in them is not updated. The switch 11 connects alternately the shift registers 9, 10 and the trigger 22 to the input of the adder 12, to another input of which receives a signal from the output of the generator 13.

: | The switch 11 and the generator 13 controls the counter 14 modulo 3 (generally K + 1, where K is the number of channels). The counter 14, the switch 11 is retracted and the new step is generated by the generator 13 simultaneously by a signal from the first output of the distributor 21 once after several clock cycles of the registers 9 and 10. Trigger 22 is set to O by the signal from the output of the first bit of the distributor 21 and 1 signal from his other exit. At the output of the adder 12, a step signal is generated, each level of which transmits information recorded in one of the registers 9, 10, or a two-level signal generated by the trigger 22.

Jlfia observation information recorded in registers 9, 10, you must connect the outputs 30 and 33 to an external oscilloscope.

The use of the signs listed in the distinctive part of the formula allows one to distinguish signals with forbidden levels; observe pulses with a duration shorter than the quantization period and random signals; output the information recorded in the analyzer shift registers to the oscilloscope, i.e.

It is useful to expand the functionality of the device in comparison with the known solutions.

Claims (3)

1. Authors certificate of the USSR 580514, cl. G 01 R 19/14, 1977. 2. US Patent 3,927,310, cl. G About F 11/00, published 1975. 3. US patent 3831149, cl. 6 01 R 15/00, published 1974 (prototype).