SU764107A1 - Sinusoidal waveform generator - Google Patents

Description

The invention relates to a radio metering technique and is intended for use as a source of calibration voltage of an alternating current of infra-low frequency. A i-generator with a stepwise approximation of sinusoidal oscillation is known, comprising a clock generator, a reversible counter or a reversing shift register, a digital-analog converter, and a source of opto-voltage 1. The generator has a proportional increase in hardware costs with an increase in the number of steps of the approximating function to reduce non-pattern. . Therefore, with nonlinear voltage distortions of less than 3-5%, these generators are rendered practically unsuitable. An infra-low frequency generator is also known, containing a series-connected reference voltage source, controllable keys and a digital-analog converter, as well as a series-connected clock generator, a first reversible counter, a decoder, an OR circuit and a second reversing counter, a logic control unit whose outputs are connected to control inputs, respectively, of the first and second reversible counters and controllable keys, the input of the logic control unit being connected to the controllable Exit decoder generator 2. The disadvantage is that to reduce the harmonic distortion of the output voltage must proportionally increase the number of decoder outputs, as well as to increase a width of reversible counters. Purpose . invention - improvement of metrological and operational parameters. The goal is achieved by the fact that a sinusoidal oscillator containing successively connected voltage source, controllable keys and a digital-to-analog converter, as well as serially connected clock generator, first reversible counter, deisfragor, OR element and second reversible counter, logic control unit The outputs to Toporo are connected to the control inputs of the first and second reversible counters and the controlled keys, respectively; control unit is connected to the controlled output of the decoder, serially-connected arithmetic unit and memory register are entered, the control inputs of which are connected to the outputs of the logic control unit, the output of the clock generator is connected to the clocked memory register input, the outputs of which are respectively connected to the first bit the inputs of the arithmetic unit and the digital input and digital analog converter, and the corresponding bits are connected to the second bit inputs of the arithmetic unit discharge bits of the second reversible counter. FIG. 1 shows a functional diagram of the generator; in fig. Figure 2 shows the curve of the dependence of the output voltage of the generator on time over a 1./4 oscillation period, where 11 -tg are the moments of transition of the approximating functions from one linear portion to another; - generator output voltage of sinusoidal oscillations. The generator contains a source 1 reference for example, keys 2, a digital-analog converter 3, a generator of 4 clock pulses, a reversible counter 5, a decryptor 6, an element OR 7, a reversible counter 8, a block 9 of logic control, an arithmetic unit 10, a memory register 11. С the outputs of the source 1 of the reference voltage through the keys 2 of the voltage of positive and negative polarity are fed to the analog input of the digital-to-analog converter 3. From the output of the generator 4 clock pulses the clock pulses enter the reversible counter 5, k It performs a direct counting of clock pulses in the first and third quarters and a reverse count in the second and fourth quarters of the output oscillation period. A decoder 6 connected to the outputs of the reversible counter 5 determines the moments ti-17 of the transition of the approximating function,. From ONE linear section to another, and the outputs of the decoder 6 through the element OR 7 are connected to the counting input of the reversible counter 8. The decoder 6 also determines the zero state of the reversing counter 5, which corresponds to the zero-crossing times of the signal to) and state counter 5, corresponding to the amplitude value of the signal (point ts), necessary for the operation of the logic control unit 9. The output code of counter 8, which characterizes the slope of the approximating function (differential increment), is algebraically added to the arithmetic unit 10 with the previous signal value stored in memory register 11, and the result of adding from the output of the arithmetic unit is fed to the input of memory register 11, where it is stored .ts for one measure. The control unit 9 sets the operation mode of the counters and the arithmetic unit: for counter 5, direct counting in the first and third quarter of the period and reversing countably the second and fourth quarter, and for counter 8, reverse counting in the first and third quarter of the period and direct the score is in the second and fourth quarters, and for the arithmetic unit 10, the arithmetic addition in the first and third quarters of the period, the arithmetic subtraction in the second and fourth quarters x. The table shows the operation of the register And and the arithmetic unit 10 with a nonlinear distortion factor of 0.8%. The shape of the output voltage for this case is shown in FIG. 2. Introduction to the memory register scheme and. an arithmetic unit allowed us to obtain a generator with a linear-step approximation of sinusoidal oscillations with irregular lengths of linear sections and reduce small distortions at the same hardware costs, which allowed us to improve the metrological and operational parameters of the generator.

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Claims (2)

1.Smelkov V.V. Digital measuring equipment of infra-low frequency. M., Energie, 1975, p. 116-124. 2.Smelkov V.V. Digital measuring equipment of infra-low frequencies. M., Energie, 1975, p. 138, fig. 3-21 (prototype).