SU762001A1 - System for reset and output of information of the state of peripheral devices of computer set - Google Patents

Description

The invention relates to the field of computer technology and can be used in functional control systems of computer systems.

Known devices for collecting information containing comparison units, memory units for storing sensor status codes, a recording unit, a unit for storing sensor state changes, a communication unit with a digital computer (DSC), a sensor address generation unit, and two registers £!].

The disadvantage of these devices is their complexity and not high enough * * performance.

The closest in technical essence to the proposed one is a device for collecting and issuing information about the state of the computing complex containing an indication unit, a storage device for status codes, including memory and control units and two groups of AND elements, a communication unit with a VVO channel. Yes-output, including exchange unit, the control unit and the buffer memory device ₄ controls the collection of results comprising analyzing unit delay block, and an information distribution unit for generating addresses, said pen input node vy · indium The unit is connected to the output of the analysis unit, the control inputs of the elements AND groups and the control input of the communication device with the input-output channel, the corresponding information inputs of which are connected to the outputs of the elements AND groups, and the output is connected to the input of the distribution unit connected to the first output through the address generation unit with information inputs of the elements And the second group and storage device'status codes [2 ^,

The disadvantage of this device is the low speed of collecting information about changes in the state of external devices.

The purpose of the invention is to increase the speed of collecting and issuing information about changes in the state of external devices

This goal is achieved by the fact that in the device containing the address generator of the external device, the output of which is connected to the first inputs of the first element And, the display unit, the storage unit of status codes and the first output of the device, the exchange control unit, the first output of which is the second output of the device, the second output - connected by the first stroke of the buffer memory, the first output

g, Г'— '' ·· · + · ·: ·> - - · · - ' ^А -''·''-. · - ·· - · · · • which is the third input of the device, and the first and the second inputs are respectively connected to the outputs <of the first and second AND elements, and the comparison circuit, the output connected to the second input of the display unit, and the first input to the output of the status code storage unit, the second input of which is connected to the first Input of the device, the second input of the comparison circuit , to the third pass of the indication unit and the first input of the second AND element, two prohibition elements are introduced, the shaper of signs of exchange, the generator impulses, a node for storing addresses of external devices, an OR element, and a synchronization node, and the output of the circuit, comparison is connected to the X first input of the first inhibit element, the output of which is connected to the second inputs of the And elements and the first input of the exchange control node, the second input of which is connected to the third input of the node storing status codes, the input of the address generator of the external device, the output of the pulse generator and the first inputs of the synchronization node and the generator of signs of exchange, the output of which is connected to the second, the input of the first ban on the element, and the second .The inputs - to the output of the OR, soot 'sponding inputs connected to the output of the second member and the ban.

...... the node for storing the addresses of external ..... devices, the first input of which is connected to the second input of the device and the third input of the exchange control node, the fourth input connected to the third input of the device, the second input of the synchronization node, the outputs of which respectively connected to the second input of the address storage unit of external devices and the first input of the second prohibition element, the second input connected to the output of the address generator of the external device. ¹

In addition, the exchange feature generator includes a constant generator, an exchange feature storage node, the output of which is the output of the driver, and the first input is connected to the output of the constant generator, and the control node, whose inputs are connected to the corresponding inputs of the driver, and the output is connected to the second input host storage prize

At the same time, a block diagram of the device is presented.

The device comprises a pulse generator 1, a driver 2 of an external device address, a first output 3 of a device, a node 4 for storing the status codes of external devices, including a driver 5 of a control signal 6, the first device 7 in a circuit, a comparison circuit 8, an indication unit 9 , the first element of the ban 10, the elements And 11 and 12, the buffer memory

13, an exchange control unit 14, a synchronization unit 15, an external device address storage unit 16, an exchange attribute generator 17, consisting of a control unit 18, a constant generator 19 and an exchange characteristic storage unit 20, an OR element 21, a second prohibition element 22, the third output 23 and the input 24 of the device ..... the second output 25 and the input 26 of the device, the outputs 27 and 28 of the synchronization unit 15.

Inputs and outputs 23-26 are connected to the standard input / output interface of a digital computer of the computer complex, input 7 and output. 3 devices are connected to the 'blocks of the built-in hardware cont. the role of external computing devices. complex.

The device operates as follows.

In the initial state, signals from the 20 generator 1 are absent, the former 2 is reset, and there are no signals at the inputs and outputs of the device. Memory 6, buffer memory 13 and node 20 are reset to zero. Node 9 displays the operational state of the YU (external device). The operation of all blocks of the device is synchronized by the signals of the generator 1.

During operation, at the inputs 24 and 26 connected to the standard interface 30 ^C At the input-output, during exchanges between the control unit and the digital computer, address codes of the 1st signal appear, identifying their address.

When a signal appears at input 24,

.. arriving at node 15, the latter performs the generation, at its output 27, of recording, polling and reset signals synchronized with the clock • frequency and controlling the operation of node 16. At the same time, the signal at output 28 prevents the address code from the former 2 through the blocking element ' that 22.

According to the code of the address of the WU, fixed in the node 16 and through the OR element 21 coming to the input of the node 18, the corresponding cell is selected. ki of the node 20, and the record on it of the constant-1 from the generator 19.

By clock signals from the generator

1 shaper 2 periodically generates at the output 3 sequentially binary codes of the address WU. Codes addresses WU arrive simultaneously at the inputs of the shaper 5, node 9, element

- And 11 and the prohibition element 22. According to the address code coming from the output 3 to the VU built-in hardware control circuits, the corresponding external device outputs to the input 7 a current state code received at the inputs of the comparison circuit 8, node 9 and And 12. The former 5 selects the WU status code obtained in the previous polling cycle from the corresponding memory cell 6 and transfers it to the input of the comparison circuit 8, which, when a state change is detected, fixes the new WU status code and displays it in node 9. Simultaneously It is the signal from the output of the comparison circuit 8 that goes to the input of the ban element 10. By the address code of this WU, which goes through the ban element 22 and the OR element 21 to the input of node 18, the corresponding cell of node 20 is sampled and polled. If this cell contains if the WU exchange flag (constant 1), recorded during the exchange of the WU with a digital computer, a prohibitory signal is input to the inhibition element 10. If there is no sign of WU exchange (zero content of the cell), then a request control signal is generated from the output of the inhibit element 10, which arrives at node 14 and at the same time permits the WU address code, which has changed its state and a new status code, to be written into the buffer memory through elements I 11 and 12 thirteen.

At the request signal, the node 14 initiates the reading of the contents of the buffer memory 13 through the output .23 in the computer of the computer complex. The node 14 in this case provides the output of information from the buffer memory 13 in accordance with the standard of the input-output interface.

Thus, the device allows to ensure the continuity of the processes of collecting information from the units of the built-in hardware control WU. At the same time, only status codes and addresses of VUs that have changed their state between adjacent polls and do not perform exchange procedures with a digital computer are issued to a digital computer, i.e. high performance and reliability are achieved. Using the device as part of a computing complex allows to increase the productivity of the complex by reducing the required time for the exchange between the digital computer and the device, to simplify the processing of transmitted information, to increase the productivity of the complex by reducing the required time for the exchange between the digital computer and the device, to simplify the processing of the transmitted information, to increase the reliability of the computing complex (due to the continuity of the collection of information about the state of the VU and increase the reliability control results), which is essential in real-time systems with stringent requirements for the reliability and reliability of information processing.

Claims (2)

Claim 1. A device for collecting and issuing information about the state of external devices of the computing complex, comprising an external device address generator, the output of which is connected to the first inputs of the first element And, the display unit, the storage unit, status codes and the first output of the device, the exchange control unit, the first output of which is the second output of the device, and the second output is connected to the first input of the buffer memory, the first output of which is the third output of the device, and the first and second inputs are respectively connected They are connected with the outputs of the first and second elements AND, and the comparison circuit, the output connected to the second input of the display unit, and the first input - to the output of the status code storage unit, the second input of which is connected to the first input of the device, the second input of the comparison circuit, the third input of the display unit And the first input of the second element And, characterized in that, in order to increase the speed of collecting information about changes in the state of external devices, two prohibition elements, a shaper of exchange signs, a pulse generator, a node are introduced into the device injured addresses of external devices, an OR element and a synchronization node, the output of the comparison circuit being connected to the first input of the first inhibit element, the output of which is connected to the second inputs of the And elements and the first input of the exchange control node, the second input of which is connected to the third input of the status code storage node, the input of the address generator of the external device, the output of the pulse generator and the first inputs of the synchronization node and the generator of signs of exchange, the output of which is connected to the second input of the first element *. and the second input - to the output of the OR element, the corresponding inputs connected to the outputs of the second ban element and the storage node- addresses of external devices, the first input of which is connected to the second input of the device and the third input of the exchange control node, the fourth input connected to the third input of the device and the second the input of the synchronization node, the outputs of which are connected respectively with the second input of the node for storing addresses of external devices and the first input of the second prohibition element, the second input connected to the output of the addresses of Tell external device. 2. Device pop. 1, characterized in that the generator of the signs of the exchange contains a constant generator, a node for storing signs of exchange, the output of which is the output of the shaper, and the first input is connected to the output of the constant generator, and the control node, the inputs of which are the corresponding inputs ^ the shaper, and the output is connected to the second input of the temple site, changing the signs of exchange.