SU754478A1 - Shift register - Google Patents

Description

The invention relates to a pulse 'technique and can be used in computing.

ί According to the main author. swith No. 588562 is known serial push-pull register containing memory elements on the MOS transistor ah, designed to store and transmit information through logic elements ^!). This register does not have sufficient speed.

The shift register contains successive bits, each of which consists of even and odd triggers, with a control unit containing an OR gate, two keys and an inverter. One input of the trigger is connected to the output of the OR element, and the other to the output of the key. Some inputs of all the OR elements are connected to clock sources, while others are connected through the first key and inverter in series with the output of the second key of this control unit. You2

the input logic block consists of two keys, the inputs of which are connected respectively to the outputs of the triggers of the last digit and the source of clock pulses, and the outputs are connected to the inputs of the output element OR. The output of the odd trigger of each digit is connected to one input of the second key of the even trigger of the next digit, and the output of the even trigger. - with one input of the second key of the odd trigger of the next digit. The second inputs of all the mentioned second keys are connected to the corresponding clock sources of £ 23. The register operates with TGP'S speed and cannot operate as a normal, slower push-pull register.

The aim of the invention is to expand the scope of the shift register by changing the speed of information movement.

This goal is achieved by

that two additional keys are introduced into the shift register, an additional OR element and a resolution bus, one of which is connected to one of the inputs of the first additional key, the other input of which is connected to the input of the shift register and the input of the second key of the odd trigger of the first digit. The output of the additional element OR is connected to the input of the second key of the even trigger of the first digit, and the inputs of the element OR, respectively, with the outputs of the first second, additional keys. The first ; the input of the second additional key is connected to another resolution bus, the second input is connected to the second clock bus, and the third is connected to the output of the odd trigger of the last digit.

FIG. I shows the functional diagram of the shift register; in fig. 2 functional memory element.

The shift register contains P bits, each of which consists of odd and even memory elements 1 and 2, additional keys 3 and 4, additional element OR 5, keys of the last digit 6 and 7, element OR of the last bit 8, output bus 9, input 10 shift register, clock tires 11 and 12, resolution buses 13 and 14, and the installation bus "O" 15.

The shift register works as follows.

Two-stroke operation mode,

In the course of operation, as information is advanced in a register, an odd memory element of the ϊth digit and an even memory element (} +1) of the discharge form one binary digit of the register in which the odd element of the th digit serves as the main one, and an even memory element (ΐ + 1 ) discharge - an auxiliary memory element.

Suppose that keys 6 and 7 and the element OR 8 are set at the input of the third digit of the register, i.e. The register contains three odd and three even memory elements.

For insertion and shift in case, select the binary code 111.

Before starting the entry of a code, all register memory elements are set to the "O" state by applying a reset pulse to the bus 15. On the bus 13 is a potential signal.

By tact T | the first least significant digit of the code G.G) is fed to the input 1O.

Since the key 3 is closed (as well as the key 6), (this digit is remembered by epemen754478

1p memory volume of 1 bit. The resolution to remember is the clock

impulse T ₁ arriving at the bus 11.

According to the stroke at the input 10 pulse

₅ does not arrive. On the bus 12 comes the clock pulse m ₂ , allowing the census of information from the memory element 1 of the category "Ιρ" in the memory element 2 of the category "2P".

By the next (second in a row), so — Ooo T ^ 'the second digit of the code ("1") is fed to the input 10. This bit is stored by the memory element 1 of the digit "ίρ". In addition, the clock pulse

15 it is allowed to copy information from memory item 2 of the category "2p" into the memory element of the 1st category "Sp".

For the next (second) counting T ₂ stroke at input 10, the signal is not received. The clock pulse T ₂ permits the copying of information from element 1 of the category Зр "through key 4 and element OR 5 into memory element 2 of category 1p" and from memory element 1 of category

25 "1p" in the 2-bit memory element "2p".

According to the next clock cycle (the third one in a row), the third digit of the code ("1") is fed to the input 10. This bit is stored by the memory element of the 1st digit.

30 "1p." In addition, according to a clock pulse, information is copied from memory element 2 of bit "1p" into memory element 1 of bit 2p and from memory element 2 of digit 2p into 35 Ment of memory 1 of bit Zp.

On the next beat T ₂ (third)

input 10 pulse arrives. The clock pulse T ₂ permits the copying of information from the memory element 1 times 40 of the row "1p" into the memory element 2 of the category "2p", from the memory element 1 of the discharge "2p" into the memory element 2 of the category! '3p ", from the memory element 1 of the category" Sp "through the key 4 and the element OR 5 45 in the memory element 2 of the category" 1P ". In this case, the entire code is recorded in the register, and it took three cycles of T ₁ and three cycles of T ₂ to enter

? G>

55

By the next (fourth) measure _; the input 10 pulse is not received. The clock pulse T <sets the “1” memory element to the 1-bit 1p memory, and allows the rewriting of information from the 2p-2 memory element to the memory 1 time in the 2p row, from the 2-bit memory element to the 2p memory element 1 digit "Зр", from the memory element 2 digit

5 754478

"Sp" through the key 7 and the element OR 8 to the input of the register, etc.

Mode of operation is tactile.

In the process of working with the promotion of information on the register, both memory elements of each register register are basic and perform the same functions.

For definiteness, we assume that the keys b and 7 and the element OR 8 are at the output of 3 bits of the register (i.e. the register contains three odd and three even memory elements). To enter and shift by register, select the binary code "111 '. Before starting to enter a code, all register memory elements are set to the" O "state by applying a reset pulse to the bus 15.

On the bus 14 is a potential signal.

According to the cycle T, the first (lowest) digit of the code ("1") is fed to the input 10. This digit is memorized by the memory element of the 1 digit "1p". The resolution for memorization is the clock pulse Τ ι,

coming on bus 11.

According to the cycle T ₂ to the input 10 receives the second digit of the code ("1"). This digit through the public key 3 and the element OR5 enters the memory element 2 of the category "1p" and is remembered last. The resolution for memorization is the clock pulse T ?, coming to the bus 12.

This clock pulse also permits the copying of information from the memory element 1 of the "1p" category into the memory element 2 of the "2p" category.

In the next clock cycle (second) T ₁ , the third code bit ("1") is input to input 10 and is remembered by memory element 1. It allows recording a clock pulse T | . The same impulse permits the copying of information from the memory element 2 of the category "2p" into the memory element of the 1 category "Sp". In this case, the entire code is recorded in the register, and it took three clocks to enter it: two clocks T | and one beat T ₂

In the next clock cycle (second) T _2, the input 10 does not receive a pulse. The clock pulse T ₂ sets the "O" state to the memory element 2 bits "1p" and allows the census of information from the memory element 1 bit "1p" to

₅ memory element 2 digits "2p", from memory item 1 digit "2p" - into memory element 2 digits "Sp", from memory item 1 discharge "Sp" through key 6. and item OR 8 - to the output of the register

Yu, etc.

Therefore, the introduction of two keys 3 and 4 and the element OR 5 allows you to use the proposed register as both push-pull and tactful.

Claims (1)

Claim Register shift aut. St. N ° 588562, 20 characterized in that, in order to expand the scope of the shift register by changing the speed of information advancement, two additional keys are added to it, an additional OR element and a resolution bus, one of which is connected to one of the inputs of the first additional key, the other input of which connected to the shift register input and the input 30 of the second key of the odd trigger of the first digit, the output of the additional element OR is connected to the input of the second key of the even trigger of the first time of the row, the inputs of the additional element 35 OR are connected respectively to the outputs of the first and second additional keys, the first input of the second additional key is connected to another resolution bus, the second input of the second additional key is connected to the second clock bus, and the third to the output of the odd trigger of the last digit.