SU750740A1 - Circular counter - Google Patents

Description

t

1 The invention relates to automation and computing and can be used in the implementation of technical means of automation and computing.

Known ring counter containing the element AND-NOT, the shift register consisting of n - series-connected trigger, and the output of the n-th trigger is connected to the input of the first trigger, the inverse outputs of all triggers are connected to the inputs of the element AND-NOT, the output of which is connected to the installation input to the unit state, the first shift register switch, the inverse output of which is connected to the installation inputs to the zero state 3, 4, and the n-th trigger register shift 1.

This ring counter is characterized by low reliability of operation, in view of the possibility of occurrence of a logical unit simultaneously on two or more outputs, a large correction time, and the presence of counting error after correction in the event of a false unit occurring in older ones.

than the information bit unit.

Also known is a ring counter containing an input bus, a reset bus, a discharge on D-flip-flops, each bit except the first contains an element I, the first input of which is connected to the inverse output of the D-flip-flop, the second input - with the output of the element AND the previous bit , the second input element And the second bit is connected to the inverse output of the D-flip-flop of the first bit, the input D of which is connected to the output of the element And

15 of the last bit, the direct output of the D-flip-flop of each bit is connected to the D-input of the D-flip-flop of the subsequent bit, the input bus is connected to the clock inputs of the D-flip-flops of bits, the installation inputs in O of which are connected to the reset bus 2.

A disadvantage of the known device is the low reliability of the operation, since in the event of failure, it is possible to spread several units in the device, and a large correction time.

The aim of the invention is to increase the reliability of the operation.

This is achieved by the fact that in the ring counter containing the input bus, reset bus, bits on D-triggers, each bit except the first one contains the first element I, the first input of which is connected to the inverse output of the D-flip-flop, the second input - with the output the first element And the previous bit, the second input of the first element And the second bit is connected to the inverse output of the D-flip-flop of the first bit whose input D is connected to the output of the first element And the last bit, the input bus is connected to the clock inputs of the D-flip-flops of all bits right my out One D-flip-flop of the first bit is connected to the D input of the D-flip-flop of the second bit, in each bit, except the first, a second AND element is entered, the OR element is added to the last bit an additional OR element, and the first bit is entered and the element NOT, in each bit except the first, the first input of the second element I is connected to the second input of the first element I, the second input of the second element I is connected to the direct output of the D-flip-flop, the output of the second element I is connected to the B of the input of the D-flip-flop subsequent discharge and with the first input of the OR element, the second input of the cat orogo is connected to the entrance

ABOUT

D-flip trigger in

Next to and from the output of the element OR subsequent discharge, the second input of the element OR of the last discharge is connected to the output of the additional element OR, the first input of which is connected to the reset bus, and the second input - to the output of the first element AND, and through the element NOT to the first input of the element AND of the first bit, the second input of the element AND of which is connected to the output of the element OR of the second bit, and the output is connected by the input of the setting to the D-flip-flop of the first bit.

The drawing shows a schematic diagram of the proposed ring counter.

The ring counter consists of O-flip-flops 1-2, 1-3, 1-4, 1-5, 1-6 1-7, And 2-3 elements, ... 2-7; 3-3, ..., 3-7; elements OR 4-3, .. 4-8, element NOT 5, element AND 6, input bus 7, reset bus 8.

The direct output of D-flip-flop 1-2 is connected to the input of D-flip-flop 1-3, the inverse output of D-flip-flop 1-2 is connected to the first inputs of the AND 2-3, 3-3 elements, the second inputs of which are connected respectively to. and inverse outputs of the D-flip-flop

ABOUT

1-3, installation input in

whom

connected to the output of the element OR 4-4 and to the first input of the element OR 4-3, the second input of which is connected to the output sjjeMeHTa AND 2-3 and to the input of the D-flip-flop 1-4, the direct and inverse outputs of which are connected respectively to the first inputs elements AND 2-4, 3-4, the second inputs of which are connected to the output of the element AND 3-3, the input to the O-D flip-flop 1-4 is connected to the output of the element OR 4-5 and to the first input of the element OR 4-4, the second input of which is connected to the output of the AND 2-4 element and to the input of the D-flip-flop 1-5, etc., the output of the AND 3-7 element is connected to the first input of the OR 4-8 element, the second the input of which is connected with a reset fault

5 8 and the output of which is connected to the input

D-flip-flop

house installation

1-7, the output of the AND 3-7 element is also connected to the input of the D-flip-flop 1-2 and through the element NOT 5 to the primary input-element AND 6, the second input of which is connected to the output of the element OR 4--3, and the input to install entrance

D-flip-flop 1-2, clock

ki in

the input of which is connected to the clock inputs of the rest triggers and with the input bus 7.

The ring counter operates as follows.

Before applying pulses to the input bus 7, the initial setting is made. If at least one of the D-flip-flops is in the state, then the output of the AND 3-7 element is logical O, and the output of the NOT 5 element is logical. G and a reset pulse received through the reset bus 8 through the OR 4 elements -8, .., 4-3 and the AND 6 element resets the D-flip-flops 1-7, ..., 1-2 to the zero state. If all D-flip-flops 1-7, ..., 1-2 are in the state O (in the initial state), then at the output of the AND 3-7 element there is a logical

and n-and the outputs of the elements And., 2-6 - logical O. 2-3, The outputs of the ring counter are respectively the output of the element And 3-7, the direct output of the D-flip-flop 1-2 and the outputs of the elements And 2-3, ... 2-7. In the initial state, the combination 10 ... O is present at the outputs of the ring counter. When the first pulse arrives on the bus 7, the trigger 1-2 goes to cocon

and at the outputs

Claims (2)

The 0100 ... O combination appears on the target counter. When the second pulse arrives on bus 7, D-flip-flop 1-2 goes to state O, and flip-flop 1-3 goes to state 0 logical 1 at the output of AND 2- 3 confirms the zero state of the trigger 1-2 through the elements 4-3, 6, at the outputs of the ring counter, the combination 0010 ... O is displayed, etc. up to the state 00 ... 01, when the next pulse arrives on the bus 7, the trigger 1-7 goes to the state O, the logical element appears at the output of the AND 3-7 element, which through the OR, ... 4-4 elements enters to the inputs of the installation in About triggers 1-7, .... 1-3. At the outputs of the ring counter, the initial combination 100 appears. O. After this, the process is repeated. In the described ring counter, it is impossible to appear at the outputs of more than one, since the outputs of the ring counter are connected via the OR elements and the AND element to the installation inputs to the zero state of the previous trigger bits and thus prohibit their false triggering of the subsequent bits not to pass. t at the outputs of the ring counter, since the second inputs of the corresponding elements AND the subsequent bits will be well. Disappearing due to a fault is also impossible, since in the case of resetting all the triggers to O, 1 First Discharge Formula of the Invention Ring counter, containing an input bus, a reset bus, bits for D-flip-flops, each bit, except for the first one, sod; Holds the first element And the first input is connected to the inverse output of the D-trigger, the second the input is with the output of the first element And the previous bit, the second input of the first element And the second bit is connected with the inverse output D-three of the first bit, the input D of which is connected to the output of the first element And the last bit, the bus is connected to clock inputs of D-flip-flops of all bits ov The direct output of the D-flip-flop of the first bit is connected to the D input of the B-tritter of the second bit, which is mainly due to the fact that, in order to increase the reliability of the function, the second element AND, the element OR, is entered into each bit except the first the last bit is an additional OR element, and the first bit is the AND element and the NOT element, in each category, except for the first, the first input of the second element And is connected to the second input of the first element And, the second input of the second element And is connected to the direct the output of the D-flip-flop, the output of the second element And is connected to D in one D-flip-flop of the subsequent discharge and with the first input of the OR element, the second input of which is connected to the installation input of the O B-flip-flop of the discharge and with the output of the OR element of the subsequent discharge, the second input of the OR element of the last bit , the first output of which is connected to the reset bus, and the second input is connected to the output of the first element AND, and through the element NOT to the first input of the AND element of the first bit, the second input of the AND element which is connected to the output of the OR element of the second bit, and the output is connected to the entrance m installation in a D-flip-flop of the first bit. Sources of information taken into account during the examination 1. USSR author's certificate No. 541291, H 0.3 K 27/00, 76 2. Gutnikov B.C. Integrated electronics in measuring devices. - L .: Energie, 1974, fig.29 (prototype).