SU720754A1 - Multichannel device for transmittion data with time-division multiplexing of channels - Google Patents

Description

(54) MULTI-CHANNEL DEVICE FOR TRANSMISSION OF INFORMATION WITH TEMPORAL SEAL OF CHANNELS

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The invention relates to electrical communication technology and can be used in multi-channel communication systems with channel compaction or time division multiplexing.

A multichannel device for transmitting information with time channel multiplexing is known, which contains the input register of the current sample, the output of which is connected to the first input of a ramp: a generating unit, connected by a signal output of a non-redundancy sample to the first input of the first And element, and the first input of the control register, values, the second input which is connected to the first information output of the deciding unit, and the output to the first input of the recording of the RAM block connected by the first readout output to the second input of the re a second block whose output is connected via the bit register to the first write input of the buffer memory block, a read generator connected to the read counter input and to the input of the first delay element connected to the first gate input of the buffer memory block, the read address input which is connected to the output of the read counter, a write generator connected by the output to the second input of the first element And to the first input of the second element And, the outputs

which are connected respectively to the first and second inputs of the OR element, connected directly to the input of the write counter, and through the second delay element to the second gate input of the buffer memory block and to the summing input of the filling control unit, the recording resolution and forced recording outputs of which are connected respectively with the third input of the first element And with the second input of the second element And, and

the output of the write counter is connected to the address input of the buffer storage block, and output register 1.

However, the known multi-channel device for transmitting information with a temporary seal channels has a low accuracy of the transmitted information.

The purpose of the invention is to increase the accuracy of the transmitted information. For this, a multichannel device for transmitting information with a temporary channel compression, containing an input register of the current sample, the output of which is connected to the first input of a solver unit, connected by a signal output of a non-redundancy sample to the first input of the first element And and the first input of the register of control values, the second the input of which is connected to the first information output of the deciding unit, and the output to the first input of the recording of the random access memory unit connected by the first readout output to the second input p block, the second output of which is connected to the first write input of the buffer memory block via a bit register, a read generator connected to the read counter input and to the input of the first delay element connected to the first gate input of the buffer memory block, read address address which is connected to the output of the read counter, a write generator connected by the output to the second input of the first element And and to the first input of the second element And, the outputs of which are connected respectively to the first and the second inputs of the OR element, which is connected directly to the input of the write counter, and through the second delay element to the second gate input of the buffer memory block and to the summing input of the filling control unit, the recording resolution and forced write outputs of which are connected respectively to the third input of the first element Both with the second input of the second element I, and the output of the write counter is connected to the write write address of the buffer memory block, and the output register, the third, fourth, fifth, sixth are entered and the seventh And elements, reversible counter and inverter, whose input is connected to the first inputs of the third and fourth And elements and connected to the output of the recording controller of the filling control unit, and the output connected to the first input of the fifth And element, with the control inputs of the recording counter, block the buffer memory, the RAM block, the read counter, with the first input of the common element AND, and with the first input of the seventh element AND, connected by the output to the subtractive input of the reversible counter, the output resolution of which is connected to about the second input of the fifth And element connected by the output to the third input of the OR element, and the third input to the output of the recording generator, while the output of the first delay element is connected to the second input of the seventh And element, with the second input of the fourth And element, the output of which is connected to to the sub input of the filling control unit connected by the high-order output to the second input of the common element I, the output of which is connected to the input of the lower-order reversible counter, and the synchronizing output of the decider unit is connected to the third input And connected to the clock input of the RAM, the second read output and the second write input of which are connected respectively to the second write input and the first output of the buffer memory block, the second input of which is connected to the output register. The drawing shows a block diagram of the proposed device. The multichannel device for transmitting information with time multiplexing of channels contains the input register 1 of the current sample, decisive block 2, block 3 of the RAM, bit register 4, register 5 of control values, block b of the buffer memory, block 7 of the filling control, generator 8 of the record , the first element is AND 9, the second element is AND 10, the OR element AND, the write counter 12, the first delay element 13, the read generator 14, the read counter 15, the second delay element 16, the output register 17, the reversing counter 18, the seventh And 19 element, bent element AND 20. h the fourth element And 21, the inverter 22, the fifth element And 23, and the third element I24. The device works as follows. Let the binary code of the next sample from some channel be input to the input of the input register 1 of the current sample, and in block 6 of the buffer memory there is at least one free cell. The filling level of block 6 is controlled by the filling control block 7, which is a substantially reversible counter, to the read input of which a read pulse is sent, and to the summing one - to write pulses. The total conversion factor of such a counter is equal to the number of cells in block 6. For all the filled cells, the output of the recording resolution of block 7 is a zero signal (corresponds to the case of overflow), and in other cases it is one. With all empty cells, there is a single signal at the output of the forced recording, and in other cases it is zero. The up / down counter 18 has a conversion factor equal to the number of cells in block 3 of the RAM. At the output of the recording resolution of the reversible counter 18, a zero signal is present if it is overflowed, and in any other case a single signal. Counter 18 is in the zero state, therefore, a single signal is present at the output of the write resolution of this counter. For the selected initial conditions, a single signal from the output of the recording resolution of block 7 opens the third element AND 24 and the fourth element AND 21, and also enters the third input of the first element AND 9. The zero signal from the output of the inverter 22 firstly closes the fifth element AND 23, the sixth element And 20 and the seventh element And 19; secondly, comes in on. the control inputs of the write counter 12 and the read counter 15, and amplify the conversion factor, equal to the total number of cells in block 6; thirdly, it goes to the control input of unit 3 and switches the input and output circuits so that the first Record input and read output open, and the second record input and read output close; fourthly, it enters the control input of block 6 and closes the second write input and read output.

This state of the blocks corresponds to the normal operation of the device. The sampling code from input register 1 is compared in decision block 2 by some kind of compression algorithm with the codes of significant samples stored in block 3, and the current sample code is written to bit register 4. As a result of the comparison, it is determined whether the sample is significant or excess. If the sample is redundant, then its code is not recorded in block 3. If it is significant, then its code through register 5 is recorded in block 3 by a write pulse from the clock output of block 2, which passes through the open third element 24, to the clock input of the block 3. In this case, at the output of the non-redundancy alarm signal of the decisive block 2, a single signal takes place which opens the first element AND 9. The write pulse from the recording generator 8 passes through the first element 9, element 11 and increases by one the contents of the counter 12 recording, and the second delay element 16 has passed during the time required for reliable operation of the counter, is fed to the second gate input of block 6. Therefore, the pulse, in correspondence with the address on the counter 12, records the sampling code from bit register 4 to the accumulator of block 6. The same pulse arrives at the summing input of block 7 and increases its state by one. With the block 6 empty, the write pulse from the writing generator 8 would pass through the second element AND 10, opened with a single signal from the output of the forced recording of block 7, and the current sample, regardless of whether it is redundant or substantial, would be recorded in block 6.

Reading into the communication channel the sampling code from the block b is performed via the output register 17 on the read pulse from the output generator of the read generator 14, which is fed to the input of the counter 15 and sets the address. The first delay element 13 delays this pulse for the time required for reliable operation of the counter, and then outputs it to the first gate input of unit 6. By this pulse, firstly, the next sample is output to the communication channel and, secondly, this pulse After passing through the open fourth element I 21, it enters the subtractive input of block 7 and decreases its state by one.

With the beginning of the segment of the active change of 0 measured processes, the number of significant samples increases dramatically, while the excess ones decrease, i.e. almost every current sample becomes significant. Consequently, all the cells of the block b are occupied (overflow case) and the output of the recording resolution of block 7 is set to a zero signal, which closes the first element AND 9, the third element AND 24 and the fourth element And 21. The single signal from the output of the inverter 22, first, opens the fifth element And 23, the sixth element And 20 and the seventh element And 19; secondly, it enters the control input of block 6 and opens the second write input and read output; thirdly, it goes to the control input of block 3 and switches the input and output circuits so that the first write input and read output are closed, and the second write input and read output open, all cells in block 3 are zeroed; fourth, it enters the control inputs of the counters of record 12 and read 15, which is equal to the volume of the new buffer memory.

To the output of the higher bit of block 7 through the sixth element AND 20 is connected, the input

5 low-order reversing counter 18, i.e. a new "control unit is formed, which has a conversion factor equal to the volume of the new" buffer memory. Moreover, the initial state of this "control unit is equal to the volume of block 6. Now decisive block 2 simply skips the current sample, and almost every sample is significant, to bit register 4, the record from which & buffer memory of the new volume is produced by impulse from the generator 8 of the record passing through the open fifth element AND 23. The entire writing and reading procedure is similar to that discussed above with the only difference that the maximum write and read address is equal to the value of the volume of the "buffer memory,

 and the read pulse passes through the seventh element AND 19 to the subtracting input of counter 18. If the volume of the new buffer memory is also filled to the limit, then a zero signal is set at the output of the recording resolution of counter 18 and the write pulse through the fifth And 23 element does not pass.

Claims (1)

As soon as the number of occupied cells in the new buffer memory becomes less than the volume of block 6 (in block 3, all the cells were reset, and the reversible counter 18 is in the zero state), a single signal is set at the output of the recording resolution of block 7, and Inverter 22 - zero. The device returns to normal operation, and the first incoming sample to input register 1 will be significant, as it is compared in decisive block 2 with zero codes from block 3. Thus, the introduction of AND elements, the inverter's inverter counter, allows Processes to increase the volume of block 6 when it overflows, and thereby reduce the loss of compressed data to zero, therefore, the accuracy of the device increases. The proposed technical solution significantly reduces the error in the recovery of compressed measured processes. A multichannel device for transmitting information with a temporary channel compression, containing an input register of the current sample, the output of which is connected to the first input of the decision block, connected by the signal output of the sample non-redundancy to the first input of the first And element, and the first input of the register of control variables, the second input of which is connected to the first information output of the decision block, and the output to the first input of the recording of the RAM block connected by the first read output to the second The second input of the decision block, the second output of which is connected to the first write input of the buffer memory block via a bit register, is connected to the input of the read counter and to the input of the first delay element connected to the first gate input of the buffer memory block, address the read input of which is connected to the output of the read counter, a write generator connected by an output to the second input of the first element And and to the first input of the second element And, the outputs of which are connected accordingly It is connected directly to the first and second inputs of the OR element connected to the counter input directly, and via the second delay element to the second gate input of the buffer memory block and to the summing input of the filling control unit, the output of the recording resolution and the forced recording of which: the third input of the first element And with the second input of the second element And, and the output of the write counter is connected to the write write address of the buffer storage block, and an output register, characterized in that The third, fourth, fifth, sixth and seventh elements And, a reversible counter and an inverter, whose input is connected to the first inputs of the third and fourth elements And, and connected to the output of the recording control of the filling control unit, and the output connected to the first input of the fifth element I, with the control inputs of the write counter, the buffer memory block, the RAM block, the read counter, with the first input of the sixth And element and the first input of the seventh And element connected to the output The input of the reversible counter, the recording resolution of which is connected to the second input of the fifth AND element connected to the third input of the OR element, and the third input to the output of the recording generator, while the output of the first delay element is connected to the second input of the seventh And element the second input of the fourth element I, the output of which is connected to the subtractive input of the filling control unit connected by the high-order output to the second input of the sixth element I, the output of which is connected to the input of the least significant time yes down counter, and the output timing deciding unit is connected to a second input of the third AND gate connected with the output of the synchronizing input operational memory unit, a second read output and a second input connected kotorogo- recording; correspondingly to the second recording input and to the first output of the buffer memory block, the second output of which is connected to the input of the output register. Sources of information taken into account in the examination 1. USSR Author's Certificate No. 50690 9, cl. G 11 C 9/00, 1972 (prototype).