SU716145A1 - Pulse shaper - Google Patents

Description

(54) PULSE FORMER

one

The invention relates to automatic control and regulation systems, in particular to pulse shapers used in voltage-to-digital converters.

. Phase pulse formers are known, using null organs to produce short pulses at the moments when a sinusoidal voltage passes its zero notes, i.e. phase 1 zero values. However, such formers cannot provide high accuracy of the formation of a phase pulse both due to the instability of the zero-body response threshold and to the occurrence of nonlinear distortions of the input sinusoidal voltage.

The closest technical solution to this invention is a phase pulse former containing a phase counter, a setpoint register, and a comparison element generating short pulses at times of comparing the current phase value with the setpoint 2. The disadvantage of this device is high accuracy of the formation of a phase pulse of sinusoidal voltage requires a high accuracy of converting sinusoidal voltage into square impulses That can not be achieved by simple methods of technical implementation.

The purpose of the invention is to increase the accuracy and stability in a wide range of external

0 conditions of its work without the use of special highly stable elements.

The goal is achieved by the fact that in the proposed pulse shaper 5 pulses are entered the block of elements AND, the shaper of the reference signal and the delay line, the information input of the block of elements AND is connected to the output of the binary account: tchik, and its control

0 input - with the output of the reference signal conditioner and through the delay line with the second input 5 binary counter, the output of the block of elements And is connected to the input of the register.

five

The drawing shows a block diagram of the proposed device.

The pulse shaper contains the limiter-normalizer 1, the transformation of the input cosine

Claims (2)

0 voltage to rectangular impulses; a binary counter 2 and an AND 3 element measuring the duration of the output pulses of the limiter — Norr 6gatel 1; register 4, which stores the measured value of the duration of the pulses; comparing code element 5; AND unit 6, 6, and a reference signal conditioner 7, which performs register correction, and a delay line 8 for resetting a double counter. In addition, in the drawing, the bus 9 of the input cosine voltage of the forms of a circuit is indicated; the body, the reference bus 10 of the pitch generator, to which the reference pulses of the external generator arrive, the bus of 11 output phase pulses. The input cosine voltage across the bus 9 is fed to the input of limiter-normalizer 1, where it is transformed from cosine-shaped into square voltage pulses, the duration of which is close, by means of a two-way limit; The half of the input voltage period, and the upper and lower levels correspond to the unit and zero levels of the logic elements used in the device. Since the cosine voltage is symmetrical about the axis; ordinates, and the operation of its limiting and normalization does not practically introduce a time shift of the converted signals, regardless of the absolute values of the limiting levels of the input signals, the middle of the output pulses of the limiter-normalizer 1 always exactly corresponds to the zero phase of the input cosine-voltage. In the device, the output phase pulses are formed by the position of the gray ones and the output pulses of the limiter are normalized to n. 1, which ensures high accuracy and stability of operation. The formation of phase pulses is carried out digitally and consists of converting the input pulse voltage of the limiter normal drive 1 into a binary number, doubled number on the register 4, dividing it into two, and dividing the current number on the register 4, dividing it into two and each time (period) in a loop, and dividing it into two and each time. Pvzu tata into a temporary position of the signals and convert the length of the pulse pulse of the limiter normalizer 1 into a binary number, these pulses are fed to one of the inputs of the element i 3, which passes the input to the second The input is the reference pulses of the external generator from the reference current 10 nE of the counting input of the dbbit counter 2. After the end of each input pulse of the limiter normalizer in the reference signal shaper 7, a single pulse is generated, which is fed to the control input of the 6-element unit I and transfers the received binary number from binary counter 2 to register 4, and then reset this counter through line 8 of the delay. The output phase pulses on the bus 11 of the device are formed by the el & tape 5 of the comparison, one of the inputs of which receives the code of the current value of the binary counter 2, and the second. - half the code value of the binary number of the register 4, which is achieved by connecting the outputs of the register 4 with the inputs of the comparison element 5 with an offset one digit to the right. When the comparison element 5 is turned on and the phase pulses appear at its output each time the current state of binary counter 2 passes half its maximum value corresponding to the duration of the output pulses of the limiter normalizer 1, i.e. exactly in the middle of each output pulse of the limiter normalizer, or when the input cosine voltage passes through the bus 9 of the driver of the zero value of its phase. The economic effect of use-. Neither the proposed technical solution is due to the above mentioned technical advantages. The invention The pulse shaper contains a binary counter, the bit outputs of which are connected to one input of the comparison element, the register outputs and the electrical 4 & I outputs are connected to the other input, the inputs of which are connected to the input and reference buses of the pulse shaper, and the output to the first input binary counter, about tl and h and y and i with the fact that, in order to improve the accuracy and stability of the fbirometer, a block of elements I, a shaper of the reference signal and a line, a delay, information input of the element I from yield of the connections of the binary counter, and its control input - with vyhodsm shaper and reference signal through a delay line to second input of binary counter, the output elements of the block and connected to the input register. Sources of information taken into account in the examination of 1, USSR Author's Certificate No. ZZH0657 Cl. G 08 C9 / 04, 1971. 2. Authors certificate of the USSR 283702, cl. G 08 C 9/04, 1969 (prototype). 716145