SU711670A1 - Arrangement for generating non-recurrent pulses - Google Patents

Description

yrojuyro RS-circuit is connected to the second run of the second logic element -NE, the third input of which is connected to the input of an additional inverto and zero output of the T-flip-flop, the first input of which through the inverter is connected to the output of the first logical element IS-NOT, and the second input is connected to the second input D-flip-flop, the first input of which is connected to the RS-flip-flop.

The electrical block diagram of the proposed device is shown in the drawing.

The device contains a bus 1 asynchronous signal bus 2 clock signals, D-flip-flop 3, RS-flip-flop 4, the first logic element 5 AND-NOT, the second logic element b AND-NOT, inverter 7, T-flip-flop 8, capacitor 9, output bus 10, additional inverter 11 and resistor 12. In the initial state, there is no asynchronous signal on bus 1, and clock 2 is fed to bus 2. The zero potential, being applied to the input of the D-flip-flop 3, S-input of the RS-flip-flop 4 and to the input of the first logic element 5 IS-NOT, supports at the output of the D-flip-flop 3 a zero potential, at the output of the RStrigger 4 and at the output of the first logic element 5 AND-NOT a single potency The zero potential of the output of the D-flip-flop 3, applied to the first input of the second logical element AND-NOT b, maintains a single potential at its output and. at the R input of the RS flip-flop 4. A logic zero level is set at the output of the inverter 7, and a single potential is maintained at the zero output of the T flip-flop, thanks to which a zero potential is maintained at the capacitor 9 and the second input of the second logic element AND-NOT.

The operation of the device is as follows: an asynchronous input signal arriving at bus 1 does not change the state of RS flip-flop 4, in connection with which a first potential appears on the first input of the T-trig 8 which does not change state T - trigger. When the first clock signal is fed to bus 2, a single potential is set at the output of D-flip-flop 3, thus preparing the analysis of the signal coincidence on the logical element b – AND –NE. Logical unit coming from. inverter output 7 on; The first input of the T-flip-flop 8, appears at its output on the trailing edge of the clock signal. A single potential is set at the output bus 10, and a zero potential at the zero output of the T-flip-flop 8 and the input of the additional inverter 11. With the filing of the second

clock signal on its trailing edge, the T-flip-flop 8 is transferred to its original state by setting a zero potential on the output bus 10, and a unit potential at the zero output. At the output of the logic element 6, the IS-NOT and the R input of the RS flip-flop 4 appear zero potential, the duration of which in time is determined by the discharge time of the capacitor 9 through the resistor 12. Under the influence of the zero potential, the RS flip-flop 4 is shifted to the opposite state which is kept by him until the end of the input asynchronous signal, thereby prohibiting the arrival of a logical unit at the first input of the T-flip-flop.

When a zero potential arrives on bus 1, RS-trigger 4 returns. to the initial state, and with the supply of the next clock pulse, the D-trigger 3 also returns to the initial state. The presence of a single potential at the output bus line 10 corresponds to the existence of a single pulse.

The device provides the generation of single pulses with a duration equal to the period of the clock signals, allows to expand the functionality of the device and simplifies further processing of the pulses. It is also possible to use the device in devices for normalizing the duration of asynchronous signals.

Claims (2)

1. Author's certificate of the USSR 528693, cl. H 03 K 3/78, 09/15/76 2. USSR author's certificate No. 501470, cl. H 03 K 3/78, 01.30.76,