SU711561A1 - Arrangement for taking logarithms and exponentiating - Google Patents

Description

The invention relates to computer technology and is intended for the logarithm and potentiation of sequential binary codes of floating point numbers. The invention may find application in sequential arithmetic devices (ALUs) with a logarithmic principle of operation, characterized by high speed (of the same order as ALUs of parallel action) —or order of one ALU clock cycle for processing a bit vector of several pairs of operands arriving in parallel. fifteen

Known devices for the logarithm and potentiation of sequential binary codes of fixed-point numbers [11. The known device 20 comprises a distributor, delay elements, OR elements, and I. However, the device is characterized by narrow functional capabilities since it cannot realize ²³ logarithms and potentiation of sequential binary codes of floating point numbers. As a result, the range of numbers represented in ALU is significantly reduced, 30 which leads to a decrease in the accuracy of calculations.

Closest to the invention in technical essence is a device containing a distributor, the input of which is connected to the start bus, a delay element, the input of which is connected to the output of the OR element, the inputs of which are connected to the outputs of the first and second elements AND, one of the inputs of the first element And is connected to the first input bus, and the other input through the element is NOT connected to the control bus, which is connected to the first input of the second element And, the second input of which through the first delay element is connected to the first input bus, w swarm delay element, the input of which is connected to the second input bus, and the output is connected to the input of the third delay element and to one of the inputs of the third AND element, the other input of which is connected to the control bus, and the output is connected to the first input of the three-input OR element, the output of which is connected to the output bus, and the second input is connected to the output of the fourth AND element, one of the inputs of which is connected to the output of the third delay element, and the other input - with the output of the element NOT, as well as a trigger, the zero input of which is connected to the bus and [2].

The aim of the invention is to expand the functionality of the device by logarithm and 5 potentiation of drama floating point numbers.

“This is achieved by the fact that in a device for logarithm and potentiation, θ containing a shift register and a trigger, the first inputs of which are connected to the installation input of the device, the distributor, the input of which is connected to the first control input of the device, distribute the first output -5 connected to the second input of the trigger, the output of which is connected to the first inputs of the AND elements of the first 'group and through the first delay element - to the first inputs of the And elements of the second corpse and the first input of the first And element, which is clocked the device’s path is connected to the input of the block of shift registers, the outputs of which are connected to the second inputs of the corresponding elements AND of the second group, the third inputs of which and the second inputs of the elements of the first group are connected to the corresponding outputs of the decoder, the inputs of which are connected to the 3Q outputs of the shift register , the outputs of the AND elements of the first group through the corresponding nodes for setting the group coefficients are connected to the inputs of the first OR element, the output of which through .35 is connected in series by the adder and the second OR element is connected output. devices, the outputs of the AND elements of the second group through the third OR element are connected to the adder input, the second control input of the device through the NOT element connected in series and the second AND element is connected to the first input of the fourth OR element, the fifth OR element, three AND elements, three delay elements are inserted 45 ki, moreover, the first information input of the device is connected to the input of the second element And, and through the second delay element, to the first input of the third element And, the second input of which 5Q and the first input of the fourth element And are connected in-torym control input devices ,. the output of element ni is connected to the first input of the fifth element And, the second output of the distributor is connected to the third input of the third element And, the output of which is connected through the fourth element OR to the second input of the shift register and the input of the third delay element, the output of which is connected to the third inputs of the nodes for setting the group coefficients , the group of outputs of the distributor through the fifth OR element is connected to the third input of the shift register, the second information input of the device through the fourth delay element is connected to the second input of the fourth second AND gate and the input of the fifth delay element whose output is connected to a second input of the fifth AND gate, whose output and the output of the fourth AND gate are connected to respective inputs of a second OR element.

Yes, the drawing shows a block diagram of the device.

The device comprises a distributor 1, a shift register 2, a decoder 3, a block 4 of shift registers, a trigger 5, a group of nodes 6 for setting coefficients, a group of elements AND 7, a group of elements AND 8, an adder 9, elements' OR 10-14, elements AND 15- 19, delay elements 20-24, element NOT 25.

The operation of the device for the logarithm and potentiation of binary numbers is as follows. In the initial state, register 2 and trigger 5 are set to zero. In the case of a logarithm, a single unit is constantly supplied to the second control input of the device, as a result of which 'elements And 17, 18 and one part of nodes' 6 of the group take part in the operation of the device. In the case of potentiation, zero is constantly supplied to the second control input of the device, as a result of which the elements And 16, 19 and the other part of the nodes of the 7 group turn on. First, consider the case of the logarithm of binary numbers. At the first stage, the first control input of the device receives a unit that is distributed at the outputs of the distributor 1 for seventeen clock cycles. Starting from the first to sixteenth measures, the first information input of the device receives the mantissa with lower digits forward. Mantissa, delayed by one beat by element 21, through the elements AND 17 and OR 13 enters the input of element 22;

while at the seventeenth cycle, zero from the second output of the dispenser 1 extinguishes the senior unit of the mantissa. From the thirteenth to sixteenth measures, from the output of the OR 14 element, a unit is issued that allows writing to register 2 from the OR 13 element from the twelfth to fifteenth digits of the mantissa. As a result of this, a unit is formed at one of the outputs of the decoder 3, which is fed to one of the elements And 7 and ya one of the elements And 8. At the seventeenth clock cycle of the signals from the first output of the distributor 1, trigger 5 is set to a single state. Unit 60 of trigger 5 permits the passage of information delayed by sixteen clock cycles by element 22. through the selected element AND 7 to the input of the corresponding node 6. The same signal 65 'from trigger 5 through element 20, the delay time of which equals the operating time of nodes 6 to the element And 15, thereby allowing the passage of clock pulses to the registers of block 4. Through the selected element And 8 and the element OR 12, information from the corresponding register of block 4 is fed to the input of the adder 9, to the other input of which through the element OR 10 information is sent from brane node 6. At the output of adder 9, the mantissa of the logarithm of the binary number is formed according to the following system of equations:

Hf

At ₅

Ub

At ₇

Uh

At ₉

U-1O

Do u ₁₂ ? at ₁₄

U45

U1b

1.01100110010x + 0.00000000001

1.01010001101X + 0.000000010111

1.00111111011X + 0.000000111011

1.00101111000x + 0.00000110.1100 ι, οοιοοοοοιοχ + 0.000010100111 Ι. 0.000000101001 + 0.000000010100 + 0.000000000111 + 0.000000000000 = X + 0.00000100100X = X + 0.00001110110 ^ = Χ · + 0.00011000010Χ = X + 0.00100001000X = X + 0.00101001001x = X + 0.00Ί10000101Χ = x + 0.00110111110x = X + 0.00111110010x = X + 0.01000100011X

The first members of the equations y ^ - y ₇ and the first two members of the equations y ₈ ~ y ₄₆ are formed at nodes 6, and the second members of the equations y, y ₇ and the third members of the equations yg - yj ₆ are recorded in the blockade registers. At the same time, each node 6 corresponds to one of the registers of block 4. From the seventeenth to the twentieth ticks, the order is placed in the lower information order to the second information input, and its sign on the twenty-first beat. This information on the element 23 is delayed by 27 clocks and through the element AND 18 is fed to the input of the element OR 11 in the form of a characteristic, ki ^ logarithm. Starting from the twenty-eighth step, the mantissa of the logarithm with the lower digits forward is removed first, then the characteristic of the logarithm is also taken with the lower digits forward, and at the last forty-eighth step, the sign of the characteristic. When potentiating, the distributor 1 starts and a unit is output at its output. Starting from the first to sixteenth clock strokes, the mantissa of the logarithm is entered into the first information input by the least significant bits, which through the elements AND 16 and OR 13 enter the input of the element 22 '. From the thirteenth to sixteenth ticks, a unit is formed at the output of the OR 14 element, which allows writing into the register 2 from the output of the OR 13 element from the thirteenth to sixteenth digits of the mantissa of the logarithm. As a result, a unit is formed at one of the outputs of the decoder 3, which is fed to the corresponding elements I 7 and I 8. At the seventeenth clock, from the first output of the distributor 1, trigger 5 is set to one, which allows the passage of the mantissa of the logarithm, delayed by sixteen cycles element 22, through the selected element And 7 to the corresponding node 6. A single signal from the trigger 5 through element 20 opens the element And 15, thereby allowing the receipt of clock pulses on the registers of block 4. Through the selected element 8 and OR gate 12 with the corresponding information block register 4 is supplied to one input of the adder, the other input of which through an OR gate 10 supplied with the output information of the selected node 6. The output of the adder 9 Pa mantissa binary number formed by the following system of equations • B:

Xj = Y + 0.01001010110U +0.0101101010011 X _£ = Y + 0.01000010101U +0.101111001101 x _s = Y + 0.00111010010U +0.110001000010 X4 = Y + 0.00110001100U +0.110010110100 x _? = Y + 0.00101000011 Y +0.110100100001 X ₆ = Y + 0.00011110111 Y + 0.110110001010 X ₇ = Y + 0.00010100111 + 0.110111101110 Xg = Y + 0.00001010011U +0.111001001100 Xt) = Y + 0.0111010011111

Hyu =. 1,00001011111U

X ₄₄ = 1.00010111101U

XP = 1.00100100001U x ₄₃ = 1.00110001000U

X ₄₄ = 1.00111110100U

X _4? = 1.01001100101U

X ₄₆ = 1.01011011010U + 0.111000110101 + 0.110110111111 + 0.110100110101 + 0.110010011011 + 0.101111101011 + 0.101100100101 + 0.101001001010

From the seventeenth to the twentieth measures, the characteristic is fed to the second information input by the younger digits, and its sign on the twenty-first measure. This information on element 23 is delayed by twenty-seven clock cycles, and through element 24 and element And 19 is supplied to element OR 11 in the form of a binary number order. Starting from the twenty-ninth measure, the mantissa and the order of the least significant bits are removed from the output of the device, and at the last forty-ninth measure - the sign of order.

In the proposed device, the expansion of its functionality is achieved by processing sequential binary codes of floating point numbers. This leads to a sharp increase in the range of binary numbers over which the device for logarithmization and potentiation operates.

According to the invention, a technical project approved by the USSR Ministry of Instrumentation has been developed. According to plan

The Ministry of Instrumentation of the USSR proposed device for the logarithmization and potentiation of binary numbers for the first time will be introduced at the enterprise NPO ¹ 'ELVA' ¹ in

1979–79 as part of a microcomputer and a tunable control logic machine. The economic effect that can be obtained by the national economy as a result of using the invention in serial production of these computers per year in the amount of 100 pieces each will be about 215 thousand rubles. in year.

Claims (2)

(54) A DEVICE FOR LOGARIFICATION AND POTENTIATION by the output of the element Ж, as well as a trigger whose zero input is connected to the installation bus 2. The aim of the invention is to enhance the functionality of the device by logarithmizing and potentiating the floating point floating point numbers. This is achieved by the fact that in a device for logarithmization and potentiation, containing a shift register and a trigger, the first inputs of which are connected to the installation input of the device, a distributor whose input is connected to the first control of the device, the first output of the distribution is connected to the second input of the trigger the output of which is connected to the first inputs of the AND elements of the first group and through the first delay element - to the first inputs of the AND elements of the second group and the first input of the first And element, which the clocking input of the device with It is united with the input of the shift register unit, the outputs of the cat are connected to the second inputs of the corresponding elements of the second group, the third inputs of which and the second inputs of the elements of the first group are connected to the corresponding outputs of the decoder, the inputs of which are connected to the outputs of the shift register, the outputs of the elements of the first group through the corresponding the current nodes for setting the coefficients of the group are connected to the inputs of the first OR element, the output of which is connected through the series-connected adder and the second OR element to the output of the device, The outputs of elements AND of the second group through the third element OR are connected to the input of the adder, the second control input of the device through the series-connected element YE and the second element AND are connected to the first input of the fourth element OR, the fifth element OR three elements AND, three delay elements are introduced. , the first information input of the device is connected to the input of the second element I and through the second delay element to the first input of the third element I, the second input of which and the first input of the fourth element I are connected to the in-torkpi control the device’s input, the output of the NOR element is connected to the first input of the fifth AND element, the second output of the distribution gel is connected to the third input of the third AND element, the output of which is connected through the fourth OR element to the second input of the shift register and the input of the third delay element whose output is connected with the third inputs of the node specifying the coefficients of the group, the group of outputs is distributed through the fifth element OR is connected to the third input of the shift register, the second information input of the device through the fourth delay element nen to a second input of the fourth AND gate and the input of the fifth delay element whose output is connected to the second input of the fifth AND gate, and whose output is the output of the fourth AND gate are connected to respective inputs of a second OR gate. The drawing shows a block diagram of the device. The device contains a valve 1, a shift register 2, a decoder 3, a block 4 of shift registers, a trigger 5, a group of nodes 6 specifying coefficients, a group of elements AND 7, a group of elements AND 8, an adder 9, elements OR 10-14, elements AND 15-19 , delay elements 20-24, NOT element 25. The operation of the device for logarithmizing and potentiating binary numbers is carried out as follows. In the initial state, register 2 and trigger 5 are set to the zero state. In the case of logarithmization, the units: 17 are constantly supplied to the second control input of the device, as a result of which the elements And 17, 18 and one part of the node b of the group take part in the operation of the device. In the case of potentiation, the second control input of the device is continuously zeroed, as a result of which the elements AND 16, 19 and the other part of the nodes 7 of the group are switched on. First, consider the case of logarithmic binary numbers. At the first stage, a unit that is distributed to the outputs of the distributor 1 is fed to the first control input of the device for seventeen cycles. Beginning from the first to the sixteenth steps, the first input of the device receives the mantissa in lower bits ahead. The mantissa, delayed by one cycle by element 21, through elements AND 17 and I. OR 13 is fed to the input of element 22; at the same time, on the seventeenth cycle, zero from the second output of the distributor 1 is used to extinguish the highest unit of the mantissa. From the thirteenth to the sixteenth cycles from the output of the element or 14, a unit is issued, which allows writing to register 2 from the element OR 13 from the twelfth to the fifteenth digit of the mantissa. As a result, a unit is formed at one of the outputs of the decoder 3. It is fed to one of the elements AND 7 and a. One of the elements of 8. At the seventeenth clock cycle of signals from the first output of the distributor 1, the flip-flop 5 is set to one. The trigger unit 5 allows the information, delayed for sixteen cycles by element 22, to pass through the selected element 7 to the input of the corresponding node 6. The same signal from trigger 5 through element 20, the delay time of which is equal to the operating time of the nodes b / e And 15, allowing the clock to pass the pulses to the registers of block 4. Through the selected element AND 8 and the OR element 12 information from the corresponding register of block 4 is fed to the input of the numerator 9, to the other input of which through the element OR 10 information is fed branded node b At the output of the adder 9, a binary number logarithm manatis is formed according to the following system of equations: 1.01100110010x + 0.00000000001 at 1.01010001101X + 0.000000010111 at 1..001111011X + 0.000000111011 vl 1.00101111000x + 0.00000110, 1100 at 1.00100000010Х + 0.000010100111 at l, 00010010111X.-f 0.000011101001 U 1.00000110101X + 0.000100110011 yg Д + 0.00000100100Х + 0.00010011100 Uts X + 0.00001110110Х - (- 0.00001110011 U -10 X- + 0, OOOilOOOOlOX + 0.00001010010 U X + 0.00100001000X + 0.00000111000, 00101001001x + 0.00000100011 y X + 0.00110000101x + 0.00000010100 4 0 / 00110111110x - f 0.00000001010 y X-fo , 00111110010x + 0.00000000011, X + 0.01000100011X + 0.00000000000 The first terms of the equation y ––, and the first two terms of the equations are formed at the nodes b, and the second terms of the equation y, - y, and third terms of the equations (, are recorded in the registers of block 4. At the same time, each node 6 corresponds to one of the registers of block 4. From the seventeenth to the twentieth clock cycles, the second information input is followed by the least significant bits ahead the first tact is his mark. This information on the element 23 is delayed by 27 cycles and through the element 18 it is applied to the input of the element OR 11 in the form of a characteristic of the logarithm. Starting from the twenty eighth clock cycle from the output of the device, the mantissa of the logarithm of the low-order bits is removed first, then the characteristic of the logarithm is also removed by the lower-order bits, and at the last forty-eighth cycle, the sign of the characteristic. At potentiation, the valve 1 is started and a unit is output at its output. Starting from the first to the sixteenth clock cycles, the first information input enters the mantissa of the logarithm with the least significant bits forwardF which, through the elements AND 16 and OR 13, enters the input of the element 22. From the thirteenth to the sixteenth clock cycles, the unit produces an entry in the register 2 from the output of the element OR 13 from the thirteenth to the sixteenth bit of the mantissa logarithms. As a result, a unit is formed on one of the outputs of the decoder 3, which is fed to the corresponding elements AND 7 and 8. At the seventeenth clock cycle, the signal from the first output of the distributor 1 trigger 5 is set to one, which permits the passage of the mantissa of the logarithm delayed by sixteen clock cycles 22, through the selected element AND 7 to the corresponding node 6. A single signal from trigger 5 through element 20 opens element 15, thereby allowing receipt of clock pulses to the registers of block 4. Through the selected element The ent And 8 and the OR element 12 information from the corresponding register of block 4 is fed to one of the inputs of the adder, to another input of which through the OR element 10 the information from the output of the selected node b is fed. At the output of the adder 9, a binary number mantissa is formed according to the following system of equations: X Y + 0.01001010110U +0.101101010011 X, Y + 0.01000010101U + 0.101111001101 Xj Y + 0, OOI1010010U +0.110001000010 X Y + 0.00110001100U +0.110010110100 Xj-Y + 0.00101000011U +0.110100100001 X (, Y + 0.00011110111U +0.110110001010 X Y + 0.00010100111U +0.110111101110 Xg U + 0.00001010011U +0.111001001100 XQ U + 0,0111010011111 Hue 1,00001011И1У + 0,111000110101 Х 1.00010111101У + 0,110110111111 X ,, 1,00100100001У + 0,110100110101 Х 1,00110001000У + 0,110010011011 Х 1,00111110100У + 0,1011101011 1 0,010001010101У X 1,00111110100У + 0,1011101011 1 0,010001010101У X 1,00111110100У + 0,1011101011 0.01,0110101010101 Х , 101100100101 Xi6 1,01011011010У + 0,101001001010 from the seventeenth to the twentieth cycles for the second information input, the lower bits for the second time give the characteristic, and for the twentieth the first clock is its knowledge. This information on the element 23 is delayed by twenty-seven cycles and through element 24 and the element I 19 is fed to the element OR 11 in the form of the order of the binary number. Starting from the twenty-ninth cycle, the mantissa is removed from the device order of time runs ahead, and at the last forty-ninth measure - a sign of order. In the proposed device, its functionality is enhanced by processing serial binary codes of floating point numbers. This leads to a sharp increase in the range of binary numbers over which the device for logarithmization and potentiation operates. According to the proposed invention, a technical project has been developed, approved by the USSR Ministry of Instrument. According to the plan of the USSR Minpribor, the proposed device for logarithmization and potentiation of binary numbers will be introduced for the first time at the enterprise NPO ELVA in 1979-79. as part of a micro-computer and a tunable control logic mat. The economic effect that can be obtained by the national economy as a result of using the invention for the mass production of these computers per year in an amount of 100 pieces each will be about 215 thousand rubles. in year. An apparatus for logarithmization and potentiation comprising a shift register and a trigger, the first inputs of which are connected to the installation input of the device, a distributor whose input is connected to the first control input of the device, the first output of the distributor is connected to the second input of the trigger, the output of which is connected to the First inputs elements of the first group and, through the first element of the delay, with the first inputs of the elements of the second group and the first input of the first element, through which the clock input device and is connected to the input of the shift register unit, the outputs of which are connected to the second inputs of the corresponding elements of the second group, the third inputs of which and the second inputs of the elements of the first group are connected to the corresponding outputs of the decoder, the inputs of which are connected to the outputs of the shift register, the elements And the first group through the corresponding nodes of the task of the coefficients of the group is connected to the inputs of the first OR element, the output of which through the successively central adder and the second element OR connects ian with the output device facilities, the outputs of the elements AND: 1g of the second group through the third element OR are connected to the input of the adder, the second control input of the device through the series-connected element NOT and the second element AND connected to the first EML input of the fourth element OR, which differs from the purpose of extending the functionality by logarithmization and potentiation of binary floating point numbers, the fifth OR element, three AND elements, three delay elements are entered into it, the first information input of the device is connected to the second input And through the second delay element - with the first input of the third element And whose second input and the first input of the fourth element And are connected to the second control input of the device, the output of the element is NOT connected to the first input of the fifth And element, the second distributor output is connected to the third the input of the third element AND, the output of which is connected through the fourth element OR to the second input of the shift register and the input of the third delay element, the output of which is connected to the third inputs of the nodes specifying the coefficients of the group, the group output in the distributor through the fifth OR element is connected to the third input of the shift register, the second information input of the device through the fourth delay element is connected to the second input of the fourth And element and the input of the fifth delay element, the output of which is connected to the second input of the fifth And element, and the output of the fourth element I are connected to the corresponding inputs of the second element OR, .. Sources of information taken into account during the examination 1. USSR Author's Certificate, No. 446054, cl. G 06 F 5/02, 1973. 2 „Copyright Certificate of the USSR, No. 523408, cl. G 06 F 5/02, 1974 (prototype) .. SS 0