SU708506A1 - Method of testing analogue-digital converters - Google Patents

Description

(54) METHOD FOR CONTROL OF ANALOG-DIGITAL PREVENTS / REVERSERS

imbalance conditions. Catastrophic failures of the ADC type switches of the COnstO type also do not violate the balancing conditions in the part of the input signal range, but result in the error of the ADC in magnitude corresponding to the weight of the failed digit. Thus, the known method of control does not provide detection of failures in faults of a number of ADC nodes.

The purpose of the present invention is to increase the completeness of the control.

To do this, in the method of controlling analog-to-digital converters, based on the change in the control process} of the compensating signal and comparing the compensating signal with the control signal, after the encoding process is completed, a compensating signal is formed that corresponds to the additional code relative to that obtained during the encoding, and the control signal corresponding to the differences between the voltage of the reference source of the converter and the input signal compare these signals and, in case of overshoot. compensating the control signal for the tolerance value and comparing the new control signal with the compensating signal.

Thus, the control of a workable ADC is detected in two control cycles, and the control of an inoperative one - in one or two cycles, depending on the nature of the fault.

The drawing shows a block diagram of the ADC with self-control, implementing the proposed method of controlling

The converter contains control device (CU) 1, switch 2, code-to-voltage converter 3 (PKN comparing device (SU) 4, switch 5, Ug input bus 6, control signal 7 (FCC) 7 and bus 8 9 JQ reference voltage and 10 tolerance voltage bus .on

Code Euykhody U 1 are connected to the code inputs of PKN 3, the output of which is connected to one of the inputs of SU 4. The output of switch 5 is connected to another input of the SU, 4 of SU 4 is connected to input of CI 1. The input bus 6 has been connected to J 5 signal, to - output FCC 7. To the inputs of the FCC 7 connected bus 6 input signal, output

key 8 and spike 9 of the reference voltage, also connected to the analog input of PKN 3. A bus 10 of the tolerance voltage is connected to the input of the key 8.

the equal inputs of the switch 2, the switch 5 and the key 8 are connected to the corresponding outputs of the CI 1.

The operation of the ADC is monitored as follows. After graduation

The coding process is followed by two control cycles in succession. In the first clock cycle, the switch 2 inverts the N code received in the coding process and contained in the CU register into a reverse one, according to the signal from the CU 1, resulting in the input of the SU 4 instead of the voltage U | N. D is the voltage U () L (here D is the quantum value, P is the number of bits). AT

A switch 5 is switched to the same clock and a control signal from the output of the FCC 7 is connected to the second input of SU 4 instead of the output signal Uf.

UKOHTB 2) c. In the case of a perfect balance

and in the absence of a feyf SU (UjK, p tf) Ua) i UK AN, from where the company; d (2-M). The difference, voltage on the inputs of the control system in the first control cycle is equal to

 UkOHTp-ui:.

If AUajr. a Mjfl fault is detected. In the case of Usxcy / LO, a second control cycle is held. The signal from the CU 1 key works 8

and the counter voltage O is reduced by the magnitude of the tolerance Udop. The value of Oop is chosen in such a way as to ensure that the condition: :: AUj, y is satisfied when the ADC is intact. in the second bar.

Failure to comply with this condition indicates a faulty ADC.

Consider how the drift of SU 4 is detected with this control method. We assume that the drift voltage is applied to the second input of the SU and is summed with the input signal. Then with perfect balancing

instead of the Ugx voltage, it is encoded:

 ABOUT)

the first control tact l

and and and

C2)

Counter Contra Aruchityva that

Jcontr op

NW)

we put in (3) the value Ug U T Aud. obtained from (1): o.r, o.l,) From (1), (2) and (4) we get: UKOMTP () Voltage at the first input. SU in the control tact and (.M-) l. % XCN KOHTP- K 2U P It is obvious that in the first console one those faults of the ADC will be detected if) O, i.e. If If a large amount of ADC drift is permissible, then the value of the control signal must be increased accordingly. If the drift voltage has a polarity that coincides with the polarity of the input signal, then the faulty ADC in the first cycle can not be detected. In the second control cycle, the value and comtr decreases HiiU. If the drift value is acceptable, the value of the tolerance voltage can be defined as .JdJ | i.d If the drift value exceeds the permissible value, then in the second control cycle. which allows you to fail. .ALO. Let us consider how, with this method of control, failures of the type of concurrent bit perceivers of the ADCs are applied. Let the failure occur in the higher order master. Then, when the input signal is encoded, the higher-order trigger will be set to state 1th 1 and remain in it, but the compensating signal will remain equal to O. In the process further zavnov- 066 and:: va1PSh; The case of the input signal in the lower half of the range will be ensured, however, the output code in the higher order will be 1 instead of O. It is obvious that in the first control cycle in this case it will be fixed, which will allow You have failed ADC. Thus, no more than two additional clocks result in faults in the ADC, both due to the violation of a single signal balance, which does not lead to a violation of balance. An increase in the control portion of the ADC is achieved by a slight increase in the amount of control equipment required for the implementation of the method. The total volume of control of the equipment does not exceed 15-2% of the volume of the main one. The invention of the method of controlling analog-to-digital converters, based on the change S of the process of controlling a compensating signal and comparing a compensatory signal with a cocktail signal, is that with the aim of increasing the completeness of control, after the end of the coding process, a complex signal is formed, corresponding to the ampholes of a co-optocoupler, which is encoded at the coded signal, w ij, and the control signal, corresponding to the meager discharge and voltage of the reference source of the transducer and input th S1ggnalom, comparing these signals and, in case of exceeding kotrolshlm compensating signal, jNieHbiirajoT pilot signal by the amount of tolerance and a new pilot signal sravni.vayut with compensating.

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.. , ./, 7O85O6

fix about

Output

 Fault signal

Claims (1)

Claim A method for monitoring analog-to-digital converters, based on changing the process of controlling the compensating signal and comparing the compensating signal with the control signal, is that, in order to increase the completeness of control, after the end of the encoding process, a compensating signal corresponding to an additional code with respect to that obtained during coding, to a control signal corresponding to the difference between the voltage of the reference source of the converter and the input signal, compare these signals scale value, and in case of exceeding kotrolnym compensating signal, the pilot signal is reduced by the amount of tolerance and a new pilot signal is compared with compensating. ** '<* *,. . .708506