SU1277396A1 - Analog-to-digital converter - Google Patents

Abstract

This invention relates to the conversion of analog signals to digital code. The invention makes it possible to increase accuracy by improving the linearity of the characteristic. A feature of the proposed technical solution is to use redundant measuring codes to correct the linearity of the conversion characteristic, which is implemented using the entered sequential-approximation register, digital-to-analog converter and clock generator, the frequency of which, in self-control mode, is adjusted to meet the specified linearity requirements. 1 hp f-ly, 4 ill. (L

Description

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Claims (2)

Code 11 The invention relates to digital computing for measurement technology and is intended to convert analog values to digital codes. The purpose of the invention is to improve accuracy by improving the linearity of the A / D conversion characteristic. FIG. 1 shows the analog-digital converter circuit in FIG. 2 shows an example of implementation of a clock generator; FIG. 3 graph diagram of the algorithm of the device; in fig. 4 is a functional block diagram. Analog-to-digital converter (Fig. 1) contains input bus 1, analog switch 2 (AK), first analog storage element made on capacitor (c) 3, amplifier 4, comparison unit 5 (BS), reference voltage source 6 ( ION) key element 7 (CE), the second analog storage element made on the capacitor (C) 8, the first block of 9 key elements (BKE), the third analog storage element made on the capacitor (c) 10, the second block of 11 key elements ( BKE), shift register 12 (RS), block 13 control codes (BC), register 14 successive approximation (RPP), digital-to-analog converter 15 (DAC), clock generator 16 (TG), output buses 17, control unit 18 (WU), input bus 19 Operating mode to which the first input of unit 18 is connected. The latter contains outputs from the first the second one 20-25, the second input 26, the seventh eighth outputs 27 and 28, the third and four inputs 29 and 30, the ninth and the third outputs 31 and 32, the fifth input 33 and the test input, which is the bus Run The clock generator 16 (FIG. 2) can be performed on a comparator 34 (k), an operational amplifier 35 (OA), a resistor (n) 36, a capacitor (c) 37, a key element 38 (CE Control Block 18 (Fig. 4) made on a permanent storage device 39 (NOM), the first and second registers 40 and 41 (RG), the counter 42 conversion to three (ST), the counter 43 cycles (CTT), the trigger 44 (Tr), the imaging unit 45 pulse (F 6 An analog-to-digital converter should be built on the basis of redundant measuring codes, for example, golden-p-ratio codes. It is advisable to use a symmetric code of golden p-proportion for a variable-voltage type of variable reference. Any real number in such a code can be represented as W- where, lj is the binary coefficient, with a.1 corresponding to summing the weight of the i-ro digit, and - subtracting the weight of the i-ro bit, Yp - the weight of the i-bit bit,, 1,2, .. /, is the code parameter. In these codes, there are control relations between the weights of the bits: oi;., - ci; 0 j j. -Oi ,, + uii-, + 0. The proposed analog-to-digital converter operates in two modes: the conversion mode of the analog input value AX to the. Symmetrical n-bit code of the golden p-ratio and in the self-test mode. Conversion of the input analog value: A., JJ into the n-bit code occurs in n steps, in each of which the value of one bit of the output code is generated. In the encoding process, the analog value A is convertible (summed algebraically with a set of n reference levels U,. Formed on the memory capacitor 10. The input analog value Aj is encoded according to the ratio i., - i.a; and ,; (The 1st value of the converted voltage on (ii -) - M conversion cycle; the value of the converted voltage on the ith conversion cycle; the time constant of the discharge circuit of the capacitor 10 to the capacitor 3; the duration of the recharge process, determined by control duration impulse; a- - output signal of comparison unit 5, defined by the expression: a,. The duration of the control pulse is chosen such that the values of the voltages (1-e) are proportional to the weights of the code bits of the gold p-proportion. The calls are generated based on the sequence of output signals of the a-block of the comparison unit 5. All units of the device participate in the conversion mode, except for the control unit 13 and the sequential approximation register 14. In this mode, the analog-to-digital converter works as follows. In the first conversion step, the input analog value A. is transferred via analog switch 2 to a storage capacitor 3, which is charged to a voltage Uj proportional to the analog input signal Ay. The storage capacitors 8 and 10 are charged through the key element 7 and the second block 11 of the key elements prior to the voltage UQ from the source 6 of the reference voltage. The voltage and, through the amplifier 4, is fed to the input of the comparison unit 5. At the output of the comparison unit 5, the value of the highest bit coefficient a is formed, in accordance with the expression (3). Moreover, the value of a 1 corresponds to the summation of the first reference level U, jj ,, H of the converted voltage II, in the next conversion step, and the value of a, 1 - subtraction of the reference level U, and the converted voltage U,. The value of the bit coefficient a is entered into the shift register 12. In the second cycle, in accordance with relation (2), the voltage Uj on the capacitor 3 is formed as follows. The capacitor 10 is switched on through the block 9 of key elements into the feedback circuit of the amplifier 4 in such a way as to supply the voltage U., reverse polarity to the capacitor 3. As a result, a voltage is formed on the capacitor 3 and, -, -, ,., (1st 64 where Z 7 is the time constant of the circuit and the capacitor 10 on the capacitor 3.; t is the duration of the recharge process determined by the duration of the control pulse. A voltage U, U is formed on the capacitor 10. On the output Ci | O 1.1 block 5 comparisons in accordance with the condition (G) is formed The second bit coefficient of the output code, which is written to shift register 12. Then, at the command of control block I8, the second reference is formed: level Ug as follows. Capacitors 8 and 10 are connected in parallel through block 11 of key elements. As a result, charge is redistributed between capacitors 8 and 10 in such a way that the voltage of the second reference level "", ....,. --t ,. rb / fa. --f- /. U ,,,., (L / K {le) (le, c where V, is the time constant of the recharge circuit of capacitors 8 and 10; is constant of the time of the recharge circuit of capacitors 10 and 3; K is the coefficient associated the values of the capacitors 8 and 10. -. K t is the duration of the recharge process, determined by the duration of the control pulse. In the third cycle, the voltage is formed in the same way (on the capacitor 3. On the capacitor 10 a voltage is formed, mt -TI Uc. mU, T2 At the output of comparison unit 5, in accordance with condition (h), the value of the third bit coefficient a is output This code is written to the shift register 12. Then, using the control unit 18, the block 11 key elements, storage capacitors 8 and 10, the voltage of the third reference level (l / K () (U, T.rU ,, ..,. in the remaining (p-3) x clock cycles, the device operates in the same way.After the conversion clock cycles expire, a symmetric p-bit golden p-ratio code corresponding to the input analog value A with an accuracy of one least significant bit will be generated in register 12. The change over time and under the influence of external conditions of the parameters of analog-nodes, namely, the zero offset of amplifier 4 and comparison block 5, the ratio of the values of memory storing capacitors 8, 10 and 3, leads to an increase in the linearity error of the converter. . In the self-checking mode, the pulse frequency of the clock generator 6 is selected, which provides conversion of the input analog value A into a code with a given linearity error. The self-verification procedure consists in the repeated coding of this auxiliary signal whose value is A 0. As a result of the coding of the reference A signal. The condition: G. is added to the auxiliary signal. 1. f-, f, the current value of the frequency of the clock generator 16; the frequency of the clock pulses of the generator 16, which converts the input analog values of Ay into a code with a given linearity error. The clock frequency 16 is controlled in accordance with condition (4) using a digital-to-analog converter 1 and a sequential approximation register 14. In the self-test mode, the device is distributed as follows. On the first hit, the command of the control unit 18 in the sequential approximation register 14 establishes a code combination in which the most significant bit is significant. The code pr obtained in sequential approximation register 14 is formed by a digital-analogue converter 15 into an analog signal that controls the frequency of the clock generator 16. As a result, the frequency f of the pulse generator is set at the output of the clock generator 16. Then the capacitors 8 and 10 are charged up to the voltage: and the source 6 of the reference voltage. A reference auxiliary signal is supplied to the storage capacitor 3 via the second input of the analog switch 2. As a result, the capacitor 3 is charged before voltage. Then, the control unit 18 generates a set of micro-instructions that transform the voltage Uf into a code in the manner described. The control unit 13 analyzes every three, one, three bits of the output {the south code formed in the shift register 12. Moreover, if the linearity error of the converter does not exceed the specified value, i.e. clock frequency f, then in the output code there will be only allowed code combinations of the form 111 and If the frequency of the clock generators in the output code is in accordance with the forbidden code combinations, as indicated by the output signal of the control unit 13. If f, f., Then the most significant bit value is generated in the forbidden code combination. If f, fj, then in the forbidden code combination, the high-order value y-1 is generated, which is fed to the D input of register 14 of the successive approximation. In the second cycle of self-checking, the signal of the control unit 18 in the sequential approximation register 14 is set to one more low bit. At the same time, the most high bit remains in the one state if, and zero, if. The resulting code combination is converted by a digital-to-analog converter 15 into an analog signal controlling the frequency of the turn-on generator 16. At the output of the clock-oscillator 16, a pulse frequency fj is set. The coding of the reference auxiliary signal Ad-. Is then repeated. The self-test procedure ends when the frequency of the clock generator 16 is equal, i.e. In the 7 output code, only the allowed code combinations of the type Tl1 and 111 will be present. The algorithm of the functioning of the proposed device in accordance with the description of the work is shown in FIG. 3, where indicated: vertex 1 "is the initial installation of PC 12 and RPP 14 ;. trust 2 and 3 are charges of storage capacitors 8 and 10. from a source of reference voltage (ion) 6; verrgina 4-7 - encoding in the measured AX measured value or auxiliary signal of verzgan A - switching the bit in the sequential approximation register 14 and organizing the time delay with that necessary for establishing transients at the output of the digital-to-analog converter 15 and the clock generator 16; The control and conditional signals necessary for controlling the operation of the analog-digital converter are shown in the table. Claim 1. Analog-to-digital converter containing an analog switch, the first information input of which is an input bus, the second information input is connected to a common bus, the output is connected to the amplifier input and through the first analog storage element to a common bus, the first and second the control inputs are connected to the first and second outputs of the control unit, the first is the Input mode of which is the bus, the third and fourth outputs are connected to the first and second control inputs of the first block elements, the fifth output is connected to the control input of the key element, whose information input is connected to the first output of the source of the reference voltage, the second output of which and the output of the key element are connected to the corresponding information inputs of the second block of key elements, between which the second analog storage element is connected , the control input of the second block of the key elements is connected to the sixth output of the control unit, the first and second outputs are connected to the corresponding information inputs of the first The first block of key elements 96 between which the third analog storage element is connected, the first output of the first block of key elements is connected to the amplifier input, the second output is combined with the amplifier output and connected to the input of the comparison unit, the output of which is connected to the second input of the control unit and to the information input of the register the shift, the first and second control inputs of which are connected to the seventh and eighth outputs of the control unit, the outputs are output buses, the outputs of the three lower bits are connected to the corresponding The corresponding inputs of the code control block whose output is connected to the third input of the control block, characterized in that, in order to improve accuracy by improving linearity, the characteristics of the analog-to-digital conversion, a clock generator, a digital-to-analog converter, a serial approximation register, whose information input is entered connected to the third lowest bit of the shift register, and the first outputs are connected to the corresponding inputs of the digital-to-analog converter, the output of which is connected to the input t generator, whose output is connected to the fourth input of the control unit, the ninth and tenth outputs of which are connected to the first and second control inputs of the sequential approximation register, the second output of which is connected to the fifth input of the control unit, the sixth input of which is the bus. , 2. The converter according to claim 1, characterized in that the control unit is executed on the first and second registers, the trigger, the pulse shaper, the counting counter for three and the clock counter, the persistent storage device, the first and second address inputs of which are the first and second inputs of the block. control, the third address input is connected to the overflow output of the recalculation counter for three, the fourth address input is the third input of the control unit, the fifth address input is connected to the overflow output of the clock counter, the sixth address input is the fifth input of the control unit, the address inputs from the seventh tenth connected to the corresponding outputs of the second register, output91 The first through fourteenth ports are connected to the corresponding information inputs of the first register, the fifteenth through eighteenth outputs are connected to the corresponding information inputs of the second register, the first control input of which is the sixth input of the control unit, the second control input is connected to the inverted output of the trigger and its information input, the first control input of which is the control input BTTWW, the second control input connected to the output of the pulse driver, direct 7739610 the output is connected to the control input of the first register, the first and second outputs of which are connected to the counting and control / y, respectively: the three counters into three counters, the third and fourth outputs are connected to the counting and control inputs of the clock counter, respectively; the fourteenth are 10 respectively the sixth, fifth, second, ninth, eighth, first, seventh, third, fourth and tenth output of the control unit, while the fourteenth output of the first register is connected to the input of the importer lsa. 19 XI Mode 226 X2 BS 5 Signal 3HZ STE 42 overflow signal 429 X4 Signal BC 13 X5 Overflow STT 43 Signal RPP 14 Early. mouth PC 12 Begin mouth RPP 14 Switching AK 2 Switching KZ 7 Switching BKE 11 Y6Nach. mouth CTM 43 21 V7Commutations AK 2 Y8 Early. mouth ST, 42 28 W9 Shift in PC 12 ST10 43  - conversion mode  -  - analysis of the output. signal BC 13  - detuning transducer end of coding self-test end P switching And za15 d C 8 from ION 6 perezar C 8 and switching A. 0 CTT: CTT + 1 MIND ST account 42 22U12 Raz d C 10 on From 3 23U13 Raz d C 10 on : C 3 32U14. Shift RPP 14 one Run  -, + 1 U - and. + And ,, - U, .- Ug,.; - Prm: LJPIin FIG. 36 J7 -ABOUT - J4 iffrtfp.  Start